Samsung Electronics Co., Ltd.

Kisoo Chang

Jaehun Seo

Myeong-Cheol Kim

Cheol Kyu Kim

Siyoung Choi

YooJung Lee

Seunghoon Park

Dongchan Kim

Keunhee Bai

Junho Yoon

Gyungjin Min

Kyounghoon Han

Minjoon Park

Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Field effect transistor having fin base and at least one fin protruding from fin base

A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.

Methods for manufacturing a semiconductor device

Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

Methods of forming semiconductor devices using hard masks

Field effect transistor having fin base and at lease one fin protruding from fin base

Growing community of inventors

Yongin-si, South Korea

Kisoo Chang