International Business Machines Corporation

Globalfoundries Inc.

Stmicroelectronics Gmbh

Intermolecular, Inc.

Sematech, Inc.

Kisik Choi

Brent A Anderson

Lawrence Alfred Clevenger

Nicholas Anthony Lanzillo

Christopher J Penny

Robert Russell Robison

Ruilong Xie

Takashi Ando

Vijay Narayanan

Hoon Sik Kim

Eduard Albert Cartier

Kangguo Cheng

Koichi Motoyama

Junli Wang

Julien Frougier

Su Chen Fan

Chanro Park

Somnath Ghosh

Sagarika Mukesh

Choonghyun Lee

Paul Raymond Besser

Albert Manhee Chu

Richard Alan Haight

Matthew Warren Copel

Changhwan Choi

Devika Sarkar Grant

Chih-Chao Yang

Tenko Yamashita

Veeraraghavan S Basker

Carl John Radens

Dechao Guo

Shom Ponoth

Balasubramanian Pranatharthiharan

Hosadurga K Shobha

Jinping Liu

Cornelius Brown Peethala

Stuart A Sieg

Olov B Karlsson

Huimei Zhou

Albert M Young

Joe Lee

Kenneth Chun Kuen Cheng

Amol Ramesh Joshi

Ashish Bodke

Zhendong Hong

Usha Raghuram

Alexander Reznicek

Bruce Bennett Doris

Theodorus E Standaert

Nicolas J Loubet

Shogo Mochizuki

Mukta G Farooq

Ajey Poovannummoottil Jacob

Son Van Nguyen

Takeshi Nogami

Benjamin David Briggs

Fee Li Lie

Prashant Majhi

Christian Lavoie

Reinaldo Ariel Vega

Xiuyu Cai

Bin Yang

Min Gyu Sung

Paul Michael Solomon

Andrew Mark Greene

Hiroaki Niimi

Kevin Shawn Petrarca

Zhen Zhang

Roy Rongqing Yu

Ravikumar Ramachandran

Guillaume Bouche

Huiming Bu

Ashim Dutta

Muthumanickam Sankarapandian

Pierre Morin

Paul Charles Jamison

John Christopher Arnold

Michael John Hargrove

Andy C Wei

Murat Kerem Akarvardar

Srikanth Balaji Samavedam

George Jonathan Kluth

Rishikesh Krishnan

Husam N Alshareef

Mark V Raymond

Robert J Miller

Edward L Haywood

John Greg Massey

Seung-Chul Song

Richard J Carter

Kai Zhao

Gangadhara Raja Muthinti

Iqbal Rashid Saraf

Victor W C Chan

Albert Sanghyup Lee

Jason Cantone

Wing L Lai

Byoung Hun Lee

Craig Henry Huffman

An approach for forming semiconductor structure composed of one or more stacked semiconductor devices with a first semiconductor device on a substrate, a first interconnect wiring structure over the first semiconductor device, a second interconnect wiring structure under a second semiconductor device joined to the first interconnect wiring structure, and a third interconnect wiring structure on the second semiconductor device where the first semiconductor device and the second semiconductor device are each one of a memory device or a logic device. The approach includes each of the first interconnect wiring structure, the second interconnect wiring structure, and the third interconnect wiring structure with a contact pitch to the first semiconductor device and to both sides of the second semiconductor device that is less than one hundred nanometers.

Stacked semiconductor devices with topside and backside interconnect wiring

A semiconductor device includes a first buried power rail (BPR) disposed through etch stop layers and a second BPR disposed in direct contact with the first BPR, where the first BPR has a larger critical dimension (CD) than the second BPR. A bottom surface of the first BPR directly contacts a via-to buried power rail (VBPR) contact. Source/drain contacts (CA) are disposed adjacent the VBPR contact and source/drain regions collectively defining middle-of-line (MOL) components. Back-end-of-line (BEOL) components are then constructed adjacent to the MOL components, and the MOL and BEOL components bond to a carrier wafer. The second BPR is then constructed on the carrier wafer.

Buried power rail at tight cell-to-cell space

According to the embodiment of the present invention, a semiconductor device includes a first source/drain and a second source/drain. A first source/drain contact includes a first portion and a second portion. The first portion of the first source/drain contact is located directly atop the first source/drain. The second portion of the first source/drain contact extends vertically past the first source/drain. The first source/drain is in direct contact with three different sides of a first section of the second portion of the first source/drain contact.

Via to backside power rail through active region

A semiconductor device includes a field effect transistor (FET). The FET includes a gate and a first source or drain (S/D) region. A frontside S/D contact may be connected to and extend vertically upward from a top surface of the first S/D region. The FET further includes a second S/D region. The second S/D region includes a conduit liner and an inner column internal to the conduit liner that extends below a bottom surface of the wraparound gate. A backside S/D contact may be connected to and extend vertically downward from a bottom surface of the second S/D region.

Field effect transistor with backside source/drain

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.

Semiconductor device with power via

Embodiments herein include semiconductor structures with a first source/drain (S/D) connected to a first field-effect transistor (FET) region, a second S/D connected to a second FET region, and a buried power rail (BPR) region. The BPR region may include a BPR, a first dielectric liner lining a first lateral side of the BPR region, and a second dielectric liner lining a second lateral side. The first dielectric liner isolates the BPR from the first FET region and the first S/D, and the second dielectric liner isolates the BPR from the second FET region. Embodiments may also include a contact electrically connecting the second S/D and the BPR through a second lateral side of the BPR region. The liners enable the BPR to be formed after the formation of gates and the S/Ds, so that the BPR does not cause problems during annealing processes of the gates and the S/Ds.

Buried power rail after replacement metal gate

A semiconductor structure is presented including a first source/drain (S/D) epi region having a first contact completely wrapping around the first S/D epi region, the first contact electrically connected to a backside power delivery network (BSPDN) and a second S/D epi region having a second contact directly contacting a first sidewall, a second sidewall, and a top surface of the second S/D epi region, the second contact electrically connected to back-end-of-line (BEOL) components.

Full wrap around backside contact

A buried power rail is provided in a non-active device region. The buried power rail includes a dielectric liner located on a lower portion of a sidewall and a bottommost surface of the buried power rail. A dielectric cap is located on an upper portion of the sidewall of the buried power rail as well as on a topmost surface of the buried power rail. The dielectric cap is present during the fabrication of a functional gate structure and thus the problems associated with prior art buried power rails are circumvented. The dielectric cap can be removed after the functional gate structure has been formed and a via to buried power rail (VBPR) contact structure can be formed in contact with the buried power rail. In some applications, and after a gate cut process, a gate cut dielectric structure can be formed in contact with the dielectric cap.

Self-aligned buried power rail cap for semiconductor devices

Embodiments of present invention provide a SRAM memory. The SRAM memory includes a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside, above the first and second PU transistors, that connects a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple, at the backside underneath the first and second PD transistors, that connects a first S/D region of the second PD transistor with a gate of the first PD transistor. A method of manufacturing the SRAM memory is also provided.

SRAM with backside cross-couple

A device comprises a first interconnect structure, a second interconnect structure, a first cell comprising a first transistor, a second cell comprising a second transistor, a first contact connecting a source/drain element of the first transistor to the first interconnect structure, and second contact connecting a source/drain element of the second transistor to the second interconnect structure. The first cell is disposed adjacent to the second cell with the first transistor disposed adjacent to the second transistor. The first and second cells are disposed between the first and second interconnect structures.

Backside power rails and power distribution network for density scaling

Bottom barrier free interconnects are provided. In one aspect, an interconnect structure includes: metal lines embedded in a dielectric; an interlayer dielectric (ILD) disposed over the metal lines; interconnects formed in the ILD on top of the metal lines; a barrier layer separating the interconnects from the ILD, wherein the barrier layer is absent in between the interconnects and the metal lines; and a selective capping layer disposed on the interconnects.

Bottom barrier free interconnects without voids

Provided is a semiconductor device. The semiconductor device comprises a transistor comprising a plurality of source/drain epitaxies. The semiconductor device further comprises at least one backside power rail under the transistor. The semiconductor device further comprises a backside inter-layer dielectric (ILD) located between the plurality of source/drain epitaxies and the at least one power rail. The semiconductor device further comprises a first backside contact connecting a first source/drain epitaxy to the at least one backside power rail. The semiconductor device further comprises one or more contact placeholders formed under the other source/drain epitaxies.

Self-aligned backside contact integration for transistors

Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

Single-mask alternating line deposition

Tiered-profile contacts for semiconductor devices and techniques for formation thereof are provided In one aspect, a method for forming tiered-profile contacts to a semiconductor device includes: depositing a first oxide layer over the semiconductor device; depositing a second oxide layer on the first oxide layer; patterning contact trenches through the first/second oxide layer down to the semiconductor device; isotropically etching a top portion of the contact trenches selective to a bottom portion of the contact trenches based on the second oxide layer having a greater etch rate than the first oxide layer to make the top portion of the contact trenches wider than the bottom portion; and filling the contact trenches with a contact metal(s) to form the tiered-profile contacts. Other methods to form tiered-profile contacts using sacrificial spacers as well as structures including the present tiered-profile contacts are also provided.

Tiered-profile contact for semiconductor

A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.

Semiconductor structures with backside gate contacts

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Hopewell Junction, NY, United States of America

Kisik Choi