Rambus Inc.

Kishore Ven Kasamsetty

Frederick Abbott Ware

Akash Bansal

Wayne Frederick Ellis

Wayne S Richardson

Lawrence Lai

Ely K Tsern

Brian S Leibowitz

John Welsford Brooks

Yohan Usthavia Frans

Simon Li

Todd W Bystrom

Arun Vaidyanath

Kurt T Knorpp

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Protocol for memory power-mode control

A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

Cross-threaded memory system

In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such 'microthreading' provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

Memory component with multiple command/address sampling modes

In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.

DRAM having a plurality of registers

Memory control component with dynamic command/address signaling rate

Memory control component with inter-rank skew tolerance

High capacity memory systems with inter-rank skew tolerance

Growing community of inventors

Cupertino, CA, United States of America

Kishore Ven Kasamsetty