Texas Instruments Corporation

Kishore Mishra

Khodor S Elnashar

Qinghua Chen

A Duty cycle optimized prescaler (,) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (,), one (,)to count negative edges of the clock pulse, and one (,)to count positive edges of the clock pulse. Each counter (,) output is connected to a comparator (,) which compares each counter output (,)to a prescaler setting (,). The comparators (,) outputs are input to an OR gate (,), the output of which, when, a logic 1, resets the counters(,) and toggles a flip-flop circuit (,) providing a clock output signal.

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Kishore Mishra