Micron Technology Incorporated

Kishore Kumar Muchherla

Sampath K Ratnam

Ashutosh Malshe

Peter Sean Feeley

Vamsi Pavan Rayaprolu

Harish Reddy Singidi

Mustafa Nazmi Kaynak

Sivagnanam Parthasarathy

Shane G Nowell

Jeffrey S McNeil, Jr

Michael G Miller

Karl David Schuh

Jiangang Wu

Gianni Stephen Alsasua

Akira Goda

Xiangang Luo

Renato C Padilla

James Fitzpatrick

Gary F Besinga

Jung Sheng Hoei

Giuseppina Puzzilli

Violante Moschiano

Christopher S Hale

Renato Padilla, Jr

Jianmin Huang

Mark Alan Helm

Eric N Lee

Gil Golov

Jeremy Binfet

Devin M Batutis

Niccolo' Righetti

Jonathan Scott Parry

Michael Sheperek

Preston Allen Thomson

Kevin Roy Brandt

Todd A Marquart

Daniel J Hubbard

Kulachet Tanpairoj

Larry Joseph Koudele

Yun Li

Qisong Lin

Carmine Miccoli

Huai-Yuan Tseng

Niccolo′ Righetti

Ting Luo

Dave Scott Ebsen

Bruce A Liikanen

Patrick Robert Khayat

Steven Michael Kientz

Scott Anthony Stoller

Phong Sy Nguyen

Dung Viet Nguyen

Marc S Hamilton

Lakshmi Kalpana Vakati

Tomoharu Tanaka

Ugo Russo

Walter Di Francesco

Vivek Shivhare

Sead Zildzic

Jiangli Zhu

Fangfang Zhu

Sanjay Subbarao

Saeed Sharifi Tehrani

Roland J Awusie

Nicola Ciocchini

Walter Di-Francesco

Sebastien Andre Jean

David Scott Ebsen

Jie Zhou

Giovanni Maria Paolucci

Cory M Steinmetz

Paing Z Htet

Jeffrey Scott McNeil, Jr

Shuhui Chen

Christopher Joseph Bueb

Tomoko Ogura Iwasaki

Sundararajan Sankaranarayanan

Jung-Sheng Hoei

Xu Zhang

Silvia Beltrami

Yifen Liu

Sead Zildzic, Jr

Ankit Vinod Vashi

Pushpa Seetamraju

Hong Lu

Giuseppe Cariello

Mark Ish

Reshmi Basu

Michele Incarnati

Lei Zhou

Xiangyu Tang

Fulvio Rori

Umberto Siciliani

Pitamber Shukla

Suresh Rajgopal

Lawrence Celso Miranda

Sheyang Ning

William C Filipiak

Tecla Ghilardi

A memory device includes a memory array including wordlines and at least one string of cells. Each cell of the at least one string of cells is addressable by a respective wordline. The memory device further includes control logic, operatively coupled to the memory array, to perform operations including generating gate-induced drain leakage (GIDL) with respect to the at least one string of cells, and causing a grounding voltage to be applied to a set of wordlines to ground each cell of the at least one string of cells addressable by each wordline of the set of wordlines. The grounding voltage applied to the set of wordlines enables transport of positive charge carriers generated by the GIDL. In some embodiments, the positive charge carriers neutralize a buildup of negative charge carriers generated during a seeding phase of a program refresh operation.

Program refresh with gate-induced drain leakage

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

Buffer allocation for reducing block transit penalty

Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include, responsive to receiving a read request to perform a read operation on a block of the memory device, incrementing a counter associated with the block to track a number of read operations performed on the block; setting a timer associated with the block to an initial value; determining that respective values of the counter and the timer are indicative of a minimum number of read operations performed on the block; and issuing a voltage discharge command to the block, wherein issuing the voltage discharge command results in the block reaching a ground voltage.

Mitigating slow read disturb in a memory sub-system

Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

Multiple-pass programming of memory cells using temporary parity generation

Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.

Temporary parity buffer allocation for zones in a parity group

Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

Generating semi-soft bit data during corrective read operations in memory devices

Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to access a first string of series-connected memory cells of the plurality of strings of series-connected memory cells in a first mode of operation for volatile storage of data to the first string of series-connected memory cells, and access a second string of series-connected memory cells of the plurality of strings of series-connected memory cells in a second mode of operation for non-volatile storage of respective data to each memory cell of a plurality of memory cells of the second string of series-connected memory cells

Volatile data storage in NAND memory

A method includes determining respective valid translation unit counts of a block of non-volatile memory cells over a period of time, determining a rate of change of the respective valid translation unit counts of the block of non-volatile memory cells over the period of time, comparing the rate of change of the valid translation unit counts to a bin transition rate, and based on comparing the rate of change of the valid translation unit counts to the bin transition rate, performing a media management operation on the block of non-volatile memory cells.

Data age and validity-based memory management

A victim management unit (MU) for performing a media management operation is identified. The victim MU stores valid data in a first memory device of a plurality of memory devices. A cached data item on a second memory device of the plurality of memory devices is identified. A valid-to-invalid ratio of the victim MU is compared to a threshold value. In view of comparison, it is determined whether to pad the cached data item with at least a subset of the valid data stored at the victim MU or dummy data. Based on the determination, the cached data item padded with one of at least a subset of the valid data stored at the victim MU or the dummy data is written to a target MU.

Padding cached data with valid data for memory flush commands

A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Using a common pool of blocks for user data and a system data structure

A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

Selectively programming retired wordlines of a memory device

A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

Modified read counter incrementing scheme in a memory sub-system

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

Described are systems and methods for validating read level voltage in memory devices. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: causing a read level voltage to be applied to a specified wordline of the plurality of wordlines; receiving an actual bit count reflecting a number of memory cells that have their respective threshold voltages below the read level voltage; and responsive to determining that a difference of an expected bit count and the actual bit count exceeds a predetermined threshold value, adjusting the read level voltage.

Validating read level voltage in memory devices

A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.

Workload-based scan optimization

Growing community of inventors

Fremont, CA, United States of America

Kishore Kumar Muchherla