Avago Technologies General IP (singapore) Pte. Ltd.

Hewlett-packard Development Company, L.p.

Seagate Technology Incorporated

Avago Technologies International Sales Pte. Limited

Kishore Kaniyar Sampathkumar

Saugata Das Purkayastha

Parag Ranjan Maharana

Mark Ish

Horia Cristian Simionescu

Luca Bert

Sumanesh Samanta

Parag R Maharana

Pradeep Balakrishnan

Durga Prasad Bhattarai

Shashikiran Venkatesh

Penchala Narasimha Reddy Chilakala

A method includes accessing a cache including a first cache block and setting the first cache block to a passive sub-state, where the first cache block in the passive sub-state is configured to be accessed or modified. The method also includes receiving at least one access or modification request of the first cache block and transitioning the first cache block from the passive sub-state to an active sub-state. The method also includes incrementing an ordinal cache activation count at an active cache counter in response to the transitioning, where the active cache counter is configured to track the activation counts such that oldest cache use counts are designated to be overwritten in the cache in an oldest-first fashion.

Fine-grained cache operations on data volumes

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

Caching systems and methods for page reclamation with simulated NVDRAM in host bus adapters

A method of adjusting asynchronous cache operations on a cache device includes accessing the cache device each cache window having a plurality of cache blocks, and each cache block having corresponding metadata indicating a status of the cache block. The method also includes receiving, at a first cache block, a first input/output operation and updating a first metadata of the first cache block, the first metadata being marked as dirty. The method also includes receiving, at a second cache block, a second input/output operation and updating a second metadata of the second cache block, the second metadata being marked as dirty. The method also includes grouping, in a page, the first and second input/output operations and updating, in a single operation according to the page, the first and second cache blocks according to the first and second input/output operations. The first and second metadata are then marked as non-dirty.

Page-based method for optimizing cache metadata updates

Methods, systems, and computer-readable storage media for performing scattered atomic I/O writes in a storage device. A list of block I/O write requests to be completed as an atomic unit is received from a requester with at least two of the block I/O write requests specifying non-contiguous data locations on a storage media. The plurality of block I/O write requests are buffered in a write buffer with each buffer entry marked as having an invalid state, wherein marking a buffer entry as having an invalid state prevents it from being flushed to the storage media. Upon buffering all of the plurality of block I/O writes, all of the buffer entries are marked as having a valid state at the same time. Upon marking all of the buffer entries as having a valid state, successful completion of the list of block I/O write requests is acknowledged to the requester.

Implementing scattered atomic I/O writes

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. AnHBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.

Caching systems and methods for execution within an NVDRAM environment

An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache comprises one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. Each of the cache-lines comprises a plurality of sub-cache lines. Each of the plurality of cache-lines and each of the plurality of sub-cache lines is associated with meta-data indicating one or more of a dirty state and an invalid state. The controller is connected to the memory and configured to (i) recognize sub-cache line boundaries and (ii) process the I/O requests in multiples of a size of said sub-cache lines to minimize cache-fills.

System and methods for caching a small size I/O to improve caching device endurance

An apparatus having an interface and a circuit is shown. The interface is configured to receive a request to access a memory. The request includes a hint. The circuit is configured to select a current one of a plurality of cache policies based on the hint. The current cache policy includes a number of current parameters ranging from some to all of a plurality of management parameters of a cache device. The circuit is further configured to cache data of the request based on the current cache policy.

Hint selection of a cache policy

Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing.

Cache load balancing in storage controllers

A storage subsystem can achieve more efficient I/O processing by enabling users to specify and pass out of band I/O hints comprising an object to be hinted, a hint type, and caching strategies associated with a hint type. A hinted object may be either a virtual device or a file. In addition to priority cache, hint types may include never-cache, sticky-cache, and volatile-cache. Hints may be passed via command-line or graphical-user interfaces.

Systems and methods for I/O processing using out-of-band hinting to block driver or storage controller

Methods and structure are provided for rebuilding cache data from a failed cache device based on tracking data for the failed cache device. The system includes a memory and a cache manager. The memory stores tracking data that correlates entries at a cache with logical block addresses of a logical volume. The cache manager is able to determine that a device implementing the cache has failed and to analyze the tracking data to identify logical block addresses correlated with cache entries from the failed cache device. The cache manager is further able to generate new cache entries at a new cache device, and to populate the new cache entries with data from the identified logical block addresses.

Cache rebuilds based on tracking data for cache entries

An apparatus comprising a memory and a controller. The memory may be configured to (i) implement a cache and (ii) store meta-data. The cache may comprise one or more cache windows. Each of the one or more cache windows comprises a plurality of cache-lines configured to store information. The controller is connected to the memory and configured to (A) process normal read/write operations in a first mode and (B) process special read/write operations in a second mode by (i) tracking a write followed by read condition on each of said cache windows and (ii) discarding data on the cache-lines associated with the cache windows after completion of the write followed by a read condition on the cache-lines.

System for efficient caching of swap I/O and/or similar I/O pattern(s)

A method to perform file system migration is described. The method comprises associating a source block device to a destination block device, wherein the source block device and the destination block device include a plurality of source blocks and destination blocks, respectively. At least one command for a source block from the plurality of source blocks is directed to the source block device or the destination block device based at least on the associating. Further, a destination block from the plurality of destination blocks is updated based, in part, on the at least one directed command.

File system migration

A method and system for differential backup of a logical disk of a data storage array is presented. The system comprises: a pool of physical storage space divided into a plurality of addressable memory locations; and a logical disk adapted to store metadata associated with a differential snapshot of the logical disk. The metadata comprises a mapping structure defining a sharing relationship between the differential snapshot of the logical disk and a previous snapshot of the logical disk that is arranged to serve as a baseline snapshot of the logical disk. The mapping structure is adapted to indicate disk regions of the logical disk that have changed in the differential snapshot of the logical disk with reference to the baseline snapshot of the logical disk.

System and method for differential backup

A system and method of creating a snapclone for on-line point-in-time complete backup in a virtualized storage system is disclosed. In one embodiment, a method for creating a snapclone for on-line point-in-time complete backup in a virtualized storage system includes receiving a copy operation directed to one or more identified segments of an original virtual disk, in response to the copy operation, substantially sequentially copying the one or more identified segments to a snapclone virtual disk, clearing bits in an in-memory sharing bitmap associated with already copied one or more identified segments, and writing the cleared bits in the in-memory sharing bitmap to a disk resident virtual disk metadata associated with the snapclone virtual disk upon receiving a current write I/O operation while the copy operation is in progress. The received current write I/O operation is targeting data outside the LBA range of the already copied one or more identified segments.

Growing community of inventors

Bengaluru, India

Kishore Kaniyar Sampathkumar