Intel Corporation

Candescent Technologies Corporation

Other

Shin-etsu Chemical Co., Ltd.

Candescent Intellectual Property Services, Inc.

Candescent Intellectual Property

Kishore K Chakravorty

Christopher J Spindt

Johanna M Swan

Ian A Young

David Gregory Figueroa

Johan Knall

Joseph F Ahadian

Toru Shirasaki

Brandon Barnett

Thomas P Thomas

Paul H Wermer

Debabrata Gupta

Matthew A Bonn

David Mushell

Philip J Elizondo

Grace Ng

Jueng Gil Lee

Thomas Dory

Stephanie Jeanne Oberg

Arthur J Learn

Roger W Barton

C Michael Garner

James Montague Cleeves

Larry E Mosley

Duane A Haven

Jorge Pedro Rodriguez

Ronald L Hansen

Michael Walk

Huong T Do

Colin D Stanners

Ronald S Besser

Swayambu Ramani

Henry K Yun

David Caudillo

Frank E Abboud

Ken Brown

Paul J Louris

Fariborz Nadi

A pellicle frame is provided that includes a pellicle frame bar having a cross-section with a shape that has at least one triangular recess in at least one side edge of a quadrilateral having an upper edge and a lower edge parallel to each other and a cross-sectional area of no greater than 20 mm. There is also provided a lithographic pellicle that includes a pellicle film stretched over one end face of the pellicle frame via a pellicle film adhesive, and that includes an exposure master plate adhesive on the other end face.

Pellicle frame and lithographic pellicle

A pellicle frame is provided that includes a pellicle frame bar having a cross-section with a shape that has a curved line-containing recess in at least one side edge of a quadrilateral having an upper edge and a lower edge parallel to each other and an area of no greater than 20 mm.

A pellicle frame is provided that comprises a pellicle frame bar having a quadrilateral cross-section, wherein an upper edge and a lower edge of a basic quadrilateral forming said cross-section are parallel to each other and each of side edges of the basic quadrilateral has one quadrilateral recess. There is also provided a lithographic pellicle that includes a pellicle film stretched over one end face of the pellicle frame via a pellicle film adhesive, and that includes an exposure master plate adhesive on the other end face.

Low stress reticle pellicle assemblies. In accordance with certain embodiments of the present invention, a pellicle frame of reduced stiffness is employed to reduce the stress a pellicle frame induces in a reticle plate. In other embodiments, a pellicle frame of reduced adhesive surface is employed to reduce the stress a pellicle frame induces in a reticle plate. In accordance with still other embodiments, a stress compensating frame is employed to reduce the cumulative stresses in an assembly comprising the reticle plate, pellicle and stress compensating frame.

Low stress pellicle frames and reticle pellicle assemblies

To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.

Electronic assemblies comprising ceramic/organic hybrid substrate with embedded capacitors

An integrated optoelectrical package for optoelectrical integrated circuits (ICs) is disclosed. The package includes a package substrate having contact receiving members on an upper surface. The contact receiving members are electrically connected to contacts on the lower surface. An optoelectronic receiver package and an optoelectronic transmitter package are each electrically mounted to respective first and second subsets of the contact receiving members. Input and output waveguide arrays are formed atop the substrate package and are optically coupled to the optoelectronic receiver package and the optoelectronic transmitter package, respectively. The contacts on the lower surface of the package substrate are designed to contact and engage the contact receiving members of a standard printed circuit board (PCB).

Optoelectrical package

To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one capacitor embedded in an interposer that lies between the die and a substrate. In an embodiment, the interposer is a multilayer ceramic structure that couples power and signal conductors on the die to corresponding conductors on the substrate. The capacitor is formed of at least one high permittivity layer and in an embodiment comprises several high permittivity layers interleaved with conductive layers. Alternatively, the capacitor can comprise at least one embedded discrete capacitor. Also described are an electronic system, a data processing system, and various methods of manufacture.

Electronic assemblies and systems comprising interposer with embedded capacitors

Data processing system comprising ceramic/organic hybrid substrate with embedded capacitors

Methods are provided for fabricating plated through hole conductive core substrate which eliminate the secondary step of producing a through hole in the dielectric material plugging the core through hole. In one embodiment of the method in accordance with the invention, a two-step lamination process is provided. One side of the conductive core is provided with a dielectric laminate, a portion of which flows into and coats the core through hole wall. Excess dielectric material flows out of the core through hole preventing plugging. Similarly, the other side of the conductive core is provided with a dielectric laminate, a portion of which flows into the core through hole completing the coating of the core through hole wall forming a dielectric liner. The dielectric liner insulates the conductive core through hole wall from a conductive layer deposited onto the dielectric liner forming a plated through hole.

Conductive core substrate fabrication

A package allowing both electrical and optical coupling between one or more integrated circuits and a printed circuit board (PCB) has an optical waveguide structure in addition to electrical connections. An optically active device is flip-chip bonded directly to an integrated circuit using solder bump technology. The optically active device has a lens directly attached to it to facilitate optical coupling to the optical waveguide. The integrated circuit is flip-chip bonded to a Ball Grid Array (BGA) package. The BGA package is bonded to the PCB using solder reflow technology.

Flip-chip package integrating optical and electrical devices and coupling to a waveguide on a board

The various embodiments of coaxial capacitors are self-aligned and formed in a via, including blind vias, buried vias and plated through holes. The coaxial capacitors are adapted to utilize the plating of a plated via as a first electrode. The dielectric layer is formed to overlie the first electrode while leaving a portion of the via unfilled. A second electrode is formed in the portion of the via left unfilled by the dielectric layer. Such coaxial capacitors are suited for use in decoupling and power dampening applications to reduce signal and power noise and/or reduce power overshoot and droop in electronic devices. For such applications, it is generally expected that a plurality of coaxial capacitors, often numbering in the thousands, will be coupled in parallel in order to achieve the desired level of capacitance.

Self-aligned coaxial via capacitors

A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.

Structure and method for forming a multilayer electrode for a flat panel display device

Electronic assembly comprising ceramic/organic hybrid substrate with embedded capacitors and methods of manufacture

An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

Electrode structure and method for forming electrode structure for a flat panel display

Growing community of inventors

San Jose, CA, United States of America

Kishore K Chakravorty