Qualcomm Incorporated

Kishalay Haldar

Sharon Graif

Richard Dominic Wietfeldt

Lalan Jee Mishra

Radu Pitigoi-Aron

Lior Amarilio

Navdeep Mer

Sriharsha Chakka

Chandan Pramod Attarde

Oren Nishry

Yogesh Garhewal

Viney Kumar

The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

Hang correction in a power management interface bus

A method of improving meta-channel communications over a secure digital (SD) bus between an SD host and an SD client is described. The method includes accessing, during a current data transfer over data lines of the SD bus, a first direct memory access (DMA) metadata and a second DMA metadata over a command (CMD) line of the SD bus using an enhanced SD direct command. The method also includes establishing, prior to a next data transfer over the data lines of the SD bus, a DMA configuration for the next data transfer based on the first DMA metadata and the second DMA metadata. The method further includes communicating the next data transfer over the data lines of the SD bus according to the DMA configuration.

Enhanced secure digital (SD) direct command for improved meta-channel communications

Systems, methods, and apparatus for communicating virtual GPIO information generated at multiple source devices and directed to multiple destination devices. A method performed at a device coupled to a serial bus includes generating first virtual GPIO state information representative of state of one or more physical GPIO output pins, asserting a request to transmit the first virtual GPIO state information by driving a data line of the serial bus from a first state to a second state after a start code has been transmitted on a serial bus and before a first clock pulse is transmitted on a clock line of the serial bus, transmitting the first virtual GPIO state information as a first set of bits in a data frame associated with the start code, and receiving second virtual GPIO state information in a second set of bits in the data frame.

Latency optimized I3C virtual GPIO with configurable operating mode and device skip

Aspects of the present disclosure relate to systems and methods for determining a state of a serial memory device. Certain embodiments provide a method of determining a state of a serial memory device. The method includes enabling the serial memory device using a first signal. The method further includes receiving a flag indicating a state of the serial memory device based on the enabling of the serial memory device using the first signal.

Methods and systems for serial memory device control

A method of improving throughput of a secure digital (SD) bus is described. The method includes accessing, during a data transfer over data lines of the SD bus, read metadata over a command (CMD) line of the SD bus between an SD host and an SD client with a first SD direct command. The method also includes reading a read packet over the data lines of the SD bus from the SD client with a second SD direct command. The method further includes storing the read packet in a host buffer allocated according to the read metadata.

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Bengaluru, India

Kishalay Haldar