Samsung Electronics Co., Ltd.

Kiseok Lee

Yoosang Hwang

Hui-Jung Kim

Keunnam Kim

Chan-Sic Yoon

Bong-Soo Kim

Dongoh Kim

Sunghee Han

Jemin Park

Junsoo Kim

Jiseok Hong

Junhyeok Ahn

Taehyun An

Jiyoung Kim

Hyeongsun Hong

Myeong-Dong Lee

Hyeonok Jung

Hoin Lee

Kyupil Lee

Min Hee Cho

Yoonyoung Choi

Hyungeun Choi

Wonsok Lee

Sangyeon Han

Minhee Cho

Dohy Hong

Seunguk Han

Euna Kim

Hyo-Sub Kim

Jiyoung Ahn

Seoryong Park

Satoru Yamada

Dongsoo Woo

Hyunmog Park

Chan Ho Park

Seungjae Jung

Bongsoo Kim

Huijung Kim

Minsu Lee

Seokhan Park

Hyosub Kim

Chansic Yoon

Joongchan Shin

Sangho Lee

Jongmin Kim

Jun Ho Lee

Kyunghwan Lee

Hyun-jung Kim

Eun Ah Kim

Jung-Hoon Han

Taejin Park

Eunjung Kim

Jong-Ho Moon

Sungwon Yoo

Sunghwan Kim

Kangjin Yoon

Daewon Kim

Yongseok Kim

Dongsuk Shin

Hyun-Jung Kim

Sungho Jang

Wooyoung Choi

Sohyun Park

Augustin Jinwoo Hong

Juik Lee

Sooho Shin

Kwangmin Kim

Woobin Song

Kyungwhoon Cheun

Hunkook Lee

Mintae Ryu

Ho Rim Yang

Hyuncheol Kim

Daeik Kim

Eun-Ji Kim

Woo Bin Song

Sung-Min Park

Sungil Park

Janghee Lee

Jaeho Hong

Jihun Lee

Moonyoung Jeong

Minwoo Song

Jay-Bok Choi

Wonwoo Lee

Kwanghoon Han

Myounghwan Lee

Sungyong Park

Hyeran Lee

Sung-Hwan Jang

Hyun-Sil Oh

Sungmin Jo

Chulkwon Park

Yongseok Ahn

Hokyun An

Sinseok Seo

Min Tae Ryu

Hyoungyol Mun

Dojun Byun

Byeongjoo Ku

A semiconductor device includes a substrate including an active region, a word line structure, a bit line structure on the substrate, and a bit line contact pattern configured to electrically connect a first impurity region of the active region with the bit line structure. The device includes a storage node contact on a side wall of the bit line structure, and the storage node contact is electrically connected to a second impurity region of the active region. The device includes a spacer structure on a side wall of the bit line structure, the spacer structure on a side wall of the bit line contact pattern, the spacer structure including a lower spacer structure surrounding a side surface of the lower portion, and an upper spacer structure disposed on a side surface of the upper portion. The device includes a capacitor structure electrically connected to the storage node contact.

Semiconductor device having an upper end of a lower spacer structure on a level same as or lower than a lower end of a storage node contact

A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.

Semiconductor device

A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.

Semiconductor memory device and method of manufacture

A semiconductor device includes a substrate including an active region, a word line structure crossing the active region and extending in a first direction, a bit line structure extending in a second direction, a bit line contact electrically connecting a first impurity region of the active region to the bit line structure, a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, and a contact barrier layer covering at least a portion of the bit line contact, wherein the bit line contact includes a lower portion having a first width and an upper portion on the lower portion and having a second width, the first width is greater than the second width, and the contact barrier layer covers a bottom surface and a side surface of the lower portion.

A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

Semiconductor devices having vertical channel transistor structures and methods of fabricating the same

A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

Semiconductor device having a cell separation pattern in contact with the bit line contact

A semiconductor device includes; a substrate including an active region including a first region and a second region, a bitline extending in a first direction on the substrate and electrically connected to the first region of the active region, a spacer structure disposed on a side surface of the bitline, a contact structure disposed on a side surface of the spacer structure and electrically connected to the second region of the active region and a data storage structure disposed on the contact structure and electrically connected to the contact structure. The contact structure includes; a conductive contact layer including a first portion and a second portion disposed on the first portion, a barrier layer surrounding the first portion of the conductive contact layer, and an air gap surrounding the second portion of the conductive contact layer.

Semiconductor device having an air gap surrounding a portion of a conductive contact layer

An integrated circuit device includes a substrate comprising an active region and a word line trench, a word line extending longitudinally in a first horizontal direction in the word line trench, a buried insulating layer on the word line, a conductive plug on the substrate, and a pad structure on the substrate and having a portion in contact with a top surface of the active region and a portion in contact with the conductive plug. The pad structure includes a conductive pad having a bottom surface in contact with the top surface of the active region and a pad spacer in contact with a sidewall of the conductive pad and protruding beyond an inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.

Integrated circuit device

A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

Semiconductor memory device

A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

A semiconductor memory device includes a device isolation pattern on a substrate and defining a first active section, a first storage node pad on the first active section, a word line in the substrate and extending across the first active section, a bit line on the first storage node pad and crossing over the word line, a storage node contact on one side of the bit line and adjacent to the first storage node pad, and an ohmic layer between the storage node contact and the first storage node pad. A bottom surface of the ohmic layer is rounded.

Semiconductor memory device and method of fabricating the same

An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

Semiconductor memory device including symmetrical channel patterns and wordlines

A wafer cleaning apparatus includes a base, a roller installation table installed on the base, a wafer support unit disposed at the roller installation table and having a support roller for rotatably supporting an edge of a wafer, a pressing roller installed on the roller installation table and above the wafer support unit, and configured to press opposite surfaces of the wafer, and a driving unit providing a force in a direction, crossing a direction of a central axis of the pressing roller, so that a shape of the pressing roller is deformed. The pressing roller deformed by the driving unit applies a first pressure to a central portion of the wafer and a second pressure, different from the first pressure, to an edge portion of the water.

Apparatus for cleaning wafer

A semiconductor device includes lower electrodes, a first supporter structure including first supporter patterns interconnecting the lower electrodes, wherein side surfaces of the first supporter patterns and side surfaces of the lower electrodes that are exposed by the first supporter patterns at least partially define a first open region, the first supporter patterns being spaced apart from one another, the first open region extending among the first supporter patterns in a horizontal direction, a dielectric layer covering the first supporter structure and the lower electrodes, and an upper electrode on the dielectric layer. A distance between adjacent ones of the first supporter patterns is smaller than or equal to a pitch of the lower electrodes.

Semiconductor devices having supporter structures

Growing community of inventors

Hwaseong-si, South Korea

Kiseok Lee