Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Micron Technology Incorporated

Kirubakaran Periyannan

Daniel Joseph Linnen

Jayavel Pachamuthu

Ramanathan Muthiah

Avinash Rajagiri

Preston Allen Thomson

Jagdish Sabde

Loc Tu

Dat Tran

Srikar Peesari

Shantanu Gupta

Sukhminder Singh Lobana

Yehuda Hahn

Dongxiang Liao

Ashish Ghai

Khanfer Kukkady

Eran Sharon

Theodore T Pekny

Chang Hua Siau

Niles Yang

Shrikar Bhagath

Tomer Tzvi Eliash

Sridhar Yadala

San A Phong

Rajan Paudel

Nika Yanuka

Ankitkumar Babariya

Narendhiran Cr

Nyi Nyi Thein

Gunter Knestele

Everett Lyons, Iv

Samuel A Shapero

Sowjanya Sunkavelli

Nikita Thacker

Grant Chapman Mackey

Aashish Sangoi

Naresh Battula

Hoang Huynh

Dat Dinh

Jay Dholakia

Elliott Rill

Sowjanya Tungala

Sini Balakrishnan

Elliott Peter Rill

Inez Hua

James Tom

A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

Solid-state drive secure data wiping for reuse and recycling

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Data storage device and method for identifying a failing area of memory based on a cluster of bit errors

The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nstage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nstage may include an Nfuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nelectronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Ndelay circuit coupled to the Ne-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Ne-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

Multiple stage fuse circuitry for counting failure events

Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Clamped semiconductor wafers and semiconductor devices

Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of those pixels to change the color (hue) and/or intensity (brightness) of the pixels so the object appears in the background image. In other examples, only the most significant bits of pixels in the background image are inverted (flipped). Exemplary latch-based procedures are described herein for high-speed processing on an NVM die. Multiple plane NVM die implementations are also described for massive processing.

Non-volatile memory die with bit-flip object insertion

Latch-based methods and apparatus for performing neural network weight parity detection on the die of a non-volatile memory (NVM) array to detect bit flip errors within neural network weight data are described, particularly for use with floating point number values. Upon detection of a parity error in a neural network weight, the erroneous weight is set to zero to trim the corresponding neuron from the network, thus preventing the erroneous value from significantly affecting the network, particularly in situations where the bit flip would otherwise affect the magnitude of a floating-point weight value. The exemplary latch-based procedures described herein are linear procedures that do not require logic decisions. Procedures are also described that assess an amount of degradation in the NVM array based on parity bit data collected in the latches. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

Memory device with latch-based neural network weight parity detection and trimming

Noise injection procedures implemented on the die of a non-volatile memory (NVM) array are disclosed. In one example, noise is injected into data by adjusting read voltages to induce bit flips while using feedback to achieve a target amount of information degradation. In another example, random data is iteratively combined with itself to achieve a target percentage of random 1s or 0s, then the random data is combined with data read from the NVM array. In other examples, pixels are randomly zeroed out to emulate dead charge coupled device (CCD) pixels. In still other examples, the timing, voltage, and/or current values used within circuits while transferring data to/from latches or bitlines are adjusted outside their specified margins to induce bit flips to inject noise into the data. The noise-injected data may be used, for example, for dataset augmentation or for the testing of deep neural networks (DNNs).

Data storage device with noise injection

Latch-based multiply-accumulate (MAC) operations implemented on the die of a non-volatile memory (NVM) array are disclosed. The exemplary latch-based MAC procedures described herein are linear procedures that do not require logic branches. In one example, the MAC operation uses a set of linear MAC stages, wherein each linear stage processes MAC operations corresponding to one bit of a first multi-bit multiplicand being multiplied against a second multi-bit multiplicand. Examples are provided wherein the MAC procedures are performed as part of a neural network feedforward procedure where the first multiplicand is a synaptic weight and the second multiplicand is an activation value. Multiple plane and multiple die NVM array implementations are also described for massive parallel processing.

Non-volatile memory die with latch-based multiply-accumulate components

A data storage device includes a power supply circuit configured to supply power to the data storage device. The power supply circuit includes a voltage clamp configured to operate in a conduction state in response to an over-voltage condition of the power supply circuit. The power supply circuit also includes a fuse in series with the voltage clamp. The fuse is configured to open in response to a current flow through the fuse and the voltage clamp exceeding a threshold value. The power supply circuit also includes a switching device that is configured to latch in a forward conduction mode in response to the voltage clamp operating in the conduction state. The switching device couples power from a positive voltage bus to the voltage clamp when the switching device is in the forward conduction mode.

Data storage device having over-voltage detection and protection

A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

Data storage device with data verification circuitry

A die-to-die voltage sharing process that may be implemented to overcome a charge pump failure on a memory die of a non-volatile storage device. When a charge pump failure is detected, a controller causes another memory die with a functional charge pump to generate and supply a voltage to the memory die with the failed charge pump. When the voltage is received by the memory die with the failed charge pump, the voltage may be used to perform a requested memory operation.

Voltage sharing across memory dies in response to a charge pump failure

A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.

System and method for warpage detection in a CMOS bonded array

A data storage device includes a memory device, an internal power supply, and a controller. When the data storage device is in an idle power state, the controller is configured to electrically isolate the data storage device from an external power source and draw power from the internal power supply to perform data storage operations. The power utilized for the data storage operations while the data storage device is in the idle power state may be exclusively from the internal power supply or a mixture of the internal power supply and the external power supply. The total power utilized during the idle power state is less than a threshold that is relative to the active power of the data storage device or at a fixed value.

Idle-power mitigation circuit

A non-volatile storage system includes a control circuit connected to non-volatile memory cells provides for progressive writing of data. That is, existing data is overwritten by new data without performing a traditional erase operation that changes the threshold voltage of the memory cells back to the traditional or original erase state. In one example, new data is written on top of old data using shifted threshold voltage distributions. Some embodiments include writing MLC data over SLC data, using intermediate erase threshold voltage distributions and/or automatically detecting which threshold voltage distributions are currently being used to store data.

Non-volatile storage with processive writes

Growing community of inventors

Santa Clara, CA, United States of America

Kirubakaran Periyannan