Micron Technology Incorporated

Kirthi Shenoy

Joseph M McCrate

Marco Sforzin

Brian M Twait

Danilo Caraccio

Frank F Ross

Amitava Majumdar

Greg S Hendrix

Ankush Lal

Anandhavel Nagendrakumar

Adam D Gailey

Krunal Patel

Provided is a memory system comprising a plurality of memory components. The ECC decoding is configured to construct first and second codewords from a single set of data within the plurality of memory components and perform error correction code (ECC) decoding on the first and second codewords received read from the plurality of memory components wherein the ECC decoding is configured to (i) detect random errors in the first received codeword and (ii) use data associated with the detected random errors to correct erasures in the second received codeword.

Interleaved Reed-Solomon (IRS) with collaborative decoding

Provided is an apparatus comprising a search engine that (i) receives parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produces corresponding sets of polynomial roots therefrom and a sequence detector that identifies sequences within each of the polynomial roots within the set of roots. The apparatus also includes a sequence check logic that (i) combines the identified sequences within each of the polynomial roots and (ii) performs a sequence check of the combined identified sequences to determine whether only one of the identified sequences is valid; and an error location generator that derives an error location in each of the ECC words within the set responsive to the valid sequence.

Decoder for burst correction read Solomon decoding for memory applications

Decoder for interleaved Reed-Solomon (IRS) with erasure/collaborative

In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

Error detection, correction, and media management on a dram device

Error detection, correction, and media management on a memory device

In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.

Selective per die DRAM PPR for memory device

Provided is an apparatus comprising a search engine configured to (i) receive parallel input of a set of syndrome polynomial products corresponding to a set of ECC words and (ii) produce corresponding sets of polynomial roots therefrom and a sequence detector configured to identify sequences within each of the polynomial roots within the set of roots. Also provided is sequence check logic for (i) combining the identified sequences within each of the polynomial roots and (ii) performing a sequence check of the combined identified sequences to determine whether only one of the identified sequences if valid; and an error location generator to derive an error location in each of the ECC words within the set responsive to the valid sequence.

Burst correction reed solomon decoding for memory applications

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Boise, ID, United States of America

Kirthi Shenoy