International Business Machines Corporation

Motorola Corporation

Kirk Samuel Livingston

Guy L Guthrie

William John Starke

Ravi Kumar Arimilli

Leo James Clark

Robert Alan Cargnoni

James Stephen Fields, Jr

Anthony M Reipold

Michael I Catherwood

Daniel W Pechonis

James C Nash

Kenneth L McIntyre, Jr

Larry Maturo

Donald E Horr

Chien-Yin Liu

A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.

L2 cache array topology for large cache with different latency domains

A symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors to complete without causing delay. Each processor includes a TLBI register associated with the TLB and TLBI logic. The TLBI register includes a sequence of bits utilized to track the completion of a TLBI issued by the processor at the other processors. Each bit corresponds to a particular processor across the system and the particular processor is able to directly set the bit in the register of a master processor once the particular processor completes a TLBI operation initiated from the master processor. The master processor is able to track completion of the TLBI operation by checking the values of each bit within its TLBI register, without requiring multi-issuance of an address-only barrier operation on the system bus.

Multiprocessor system with retry-less TLBI protocol

A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes). The cache array may be arranged with rows and columns of cache sectors (rows corresponding to the cache ways) wherein a given cache line is further spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array can also output different sectors of the given cache line in successive clock cycles based on the latency of a given sector.

Half-good mode for large L2 cache array topology with different latency domains

A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N&#x2212;1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.

Cache directory array recovery mechanism to support special ECC stuck bit matrix

Disclosed is a symmetric multiprocessor data processing system (SMP) that implements a TLBI protocol, which enables multiple TLBI operations from multiple processors within a partition to complete concurrently. Thus, a global TLB lock, synchronization, and TLB unlock is not necessary. When a TLBI instruction is executed, the master dynamically manages the behavior of the TLBI operation based on asynchronously snooping another TLBI. If concurrent TLBI management is required, then the master dynamically degrades the TLBI to a 'barrier' class instruction.

Multiprocessor system supporting multiple outstanding TLBI operations per partition

A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N&#x2212;1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted. Thereafter, the data is re-read from the array, and if the error was due to a hard fault (stuck bit), it will appear correct (after applying the polarity indicated by the inversion bit), since the inversion will have changed the value of the defective bit to the stuck value. The inversion bit may be part of the data itself. In this case, one of the columns in the ECC matrix corresponds to the inversion bit, and each bit in that column of the matrix is set. In the case of an ECC protected mechanism such as a system bus, once a stuck bit condition is detected, the sending device can elect to send data such that the polarity of the data for that bit is always flipped to match the logic level of the stuck value on the wire. This approach allows for full single-bit correct, double-bit detect even in the presence of a stuck bit.

Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism

A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion of the burst transaction. The present invention offers a method of terminating a burst transaction without the addition of wait states, and further allows termination to effectively interrupt the burst transaction rather than waiting for burst completion. In one embodiment, on the negation of a burst request signal during a burst transfer, external bus interface (30) terminates the burst transfer without waiting for the completion of the burst transaction.

Method and apparatus for burst protocol in a data processing system

The present invention relates in general to a data processing system (10), and more particularly to a method and apparatus for providing instruction pipe (106) status information, including fullness information, external to data processing system (10). In one embodiment, an IPIPE2 integrated circuit terminal (15) is used to serially provide a pipe depth value indicating the fullness of the instruction pipe (106). The serial protocol used with the IPIPE2 (15) terminal includes a start bit, a fetch pointer value, and a plurality of idle bits. In one embodiment, IPIPE0 (13) and IPIPE1 (14) integrated circuit terminals may indicate loading and unloading of instruction pipe (106) and may stop toggling when central processing unit (102) is in a loop mode.

Method and apparatus for providing pipe fullness information external to

A method for minimizing power consumption in a circuit is accomplished by identifying, based on the test parameters and topology information for the circuit, potential excessive power consuming sites. Next, the potential excessive power consuming sites, or potential leakage current sites, are monitored, based on the test parameters, for indeterminate logic states which result in leakage current and excessive power consumption. A report is generated detailing the locations of any leakage current sites, whereby the circuit may be modified to eliminate the leakage current sites prior to fabrication.

Method for identifying excessive power consumption sites within a circuit

A memory expansion scheme is provided which permits a program to automatically cross memory bank boundaries, without user intervention. A memory bank address register stores a value corresponding to a selected memory bank (i.e. Bank 0), in a 4-bit subfield (K-Field). In the preferred embodiment, the K-Field is implemented using six (6) bank number registers, each of which is coupled to the corresponding address register, to form a 20-bit (extended) logical address. During an effective address calculation, in the index addressing mode, a 16-bit logical offset address, stored in an offset register, is added to the 20-bit (extended) logical address, by an adder in the ALU. The adder transfers a 20-bit physical address onto an address bus, via an address buffer. When the calculated address crosses a memory bank boundary, the upper four (4) address bits (A.sub.16 -A.sub.19) are automatically updated, thereby enabling the program to cross a memory bank boundary without user intervention. Furthermore, in selected cases, the contents of the bank number register (address bits A.sub.16 -A.sub.19) are automatically updated. Thus, the memory bank expansion scheme provides the capability to automatically cross memory bank boundaries, while automatically updating the information stored in the bank number register.

Growing community of inventors

Austin, TX, United States of America

Kirk Samuel Livingston