Motorola Corporation

Kirk N Holden

Ashok H Someshwar

Renny L Eisele

B Chris DeWitt

A self-adjusting precharge level circuit for coupling to an N-channel precharged bus line. The precharge circuit comprises first, second, and third N-channel transistors and first and second inverters. The first transistor couples the bus line to a positive power supply voltage terminal during a precharge period when the voltage on the bus line falls below the positive power supply voltage minus an N-channel MOS transistor threshold. The second and third transistors together couple the bus line to a second power supply voltage terminal during the precharge period when the voltage level of the bus line rises above positive power supply voltage minus the N-channel MOS therehold, after the voltage level is sensed by the first and second inverters. Sensing and adjusting the voltage in this manner allows the circuit to maintain an N-channel precharge level on a bus which has circuits driving CMOS levels coupled to it, while dampening the voltage response and suppressing oscillation.

Self-adjusting precharge level circuit

A circuit for adding two N-bit binary numbers with an input carry bit, where N is an integer, by the carry select technique is provided. A ranked ordered plurality of section adders function in conjunction with rank ordered carry select logic circuits to initially provide two sum bits and two output carry bits for each bit position corresponding to carry input bits of zero and one, respectively. The section adders comprise full adders and are divided into at least two ranked groups in which sum bits are concurrently calculated in each group. Each full adder concurrently provides two sum bits for each rank ordered output sum bit. The rank ordered carry select logic circuits sequentially provide carry select bits which are used by the full adders to select one of the two sum bits as the output sum bit. Two output carry bits are concurrently provided by each group. One of the two output carry bits of the lowest ranked group is provided as a half carry output bit in response to the carry input bit. One of the two output carry bits of the highest ranked group is provided as the sum output carry bit in response to the half carry bit of the lower ranked group.

N-bit carry select adder circuit with double carry select generation

An n-bit adder circuit, where n is an integer, for providing carry select addition of two input numbers is provided. A rank ordered plurality of section adders each have a plurality of full adders. Each full adder utilizes a single half adder to provide two sum bits which are coupled to a multiplexer which is an integral part of each section adder. One sum is for a carry-in and the other sum is for no carry-in. A method of minimizing logic circuitry which provides carry bits and carry sum select bits is provided. The carry bits and carry sum select bits control which of the two sums are provided by each section adder. By providing the carry bits and carry sum select bits in complement form every other order of section adder, logic circuitry and logic gate delays are minimized.

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Austin, TX, United States of America

Kirk N Holden