Hewlett Packard Enterprise Development LP

Kirk M Bresniker

Dejan S Milojicic

Paolo Faraboschi

John Paul Strachan

Chris I Dalton

Greg Astfalk

The disclosure provides for systems and methods for improving bandwidth and latency associated with executing data requests in disaggregated memory by leveraging usage indicators (also referred to as usage value), such as 'freshness' of data operators and processing “gravity” of near memory compute functions. Examples of the systems and methods disclosed herein generate data operators comprising near memory compute functions offloaded proximate to disaggregated memory nodes, assign a usage value to each data operator based on at least one of: (i) a freshness indicator for each data operators, and (ii) a gravity indicator for each near memory compute function; and allocate data operations to the data operators based on the usage value.

Freshness and gravity of data operators executing in near memory compute in scalable disaggregated memory architectures

A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.

Methods and systems for computing in memory

According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.

Capability enforcement controller

Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

Capability enforcement processors

A system including a driver circuit. The driver circuit is configured to provide first output signals in a first mode for electrical signaling and second output signals in a second mode for optical signaling. The driver circuit is configured to provide the first output signals in the first mode with at least one of a lower frequency and higher power and the second output signals in the second mode with at least one of a higher frequency and lower power.

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Granite Bay, CA, United States of America

Kirk M Bresniker