Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Kirk Hwang

Martin Aureliano Hassner

Jeffrey Joesph Dobbek

Sridhar Chatradhi

Jonathan Darrel Coker

Satoshi Yamamoto

Roger William Wood

Bruce Alexander Wilson

Spencer W Ng

Michael Anthony Moser

Gary Allan Herbst

Masaki Kohno

Vipul Srivastava

Kei Akiyama

Naoyuki Minami

Hung Phan

Data storage devices using a two-level ECC scheme are described. Embodiments of the invention allow the recovery of sectors in a squeezed group of tracks in a that includes both a single track level ECC scheme and a track band ECC scheme that functions across the set of tracks in the band. The track band ECC scheme uses additional parity information calculated using input data from multiple tracks to allow correction across tracks.

Track-band squeezed-sector error correction in magnetic data storage devices

Data storage devices are described with an ECC system that generate additional on-demand ECC information for a previously written track to provide for correction of data errors in the track and thereby avoid having to rewrite the track. Embodiments of the invention address the squeeze-error problem that arises when writing the next (second) track in a sequence causes errors to be introduced in the adjacent previously written (first) track. In alternative embodiments the existence of the data errors in the first track can be detected by reading the track or by estimating the number of likely errors using head position data measured while writing the first and second tracks. The additional on-demand ECC information can be written on any track that is available.

Error correction with on-demand parity sectors in magnetic data storage devices

A technique for recovering of 'squeezed' sectors in a set of sequential sectors such as are used in Shingled Magnetic Recording (SMR) is described. Embodiments of the invention use a programmable erased sector recovery scheme, which is a concatenation of a 'Cauchy-type' track erasure correction code, together with a media-error correction code that generates N-weighted parity-sectors per track and is capable of replacing up to N-erased sectors per track in any possible combination.

Scalable repair block error correction for sequential multiple data blocks in a magnetic data storage device

A disk drive is described with a single servo master timer that is used to control timing critical signals such as servo gate, SAM windows, channel power save, PREAMP power save and so on. The master timer is adjusted to compensate for SAM detection errors (early, late or missed) and provides improved servo timing quality. In an embodiment the adjustable master timer can be selectably clocked by either the DLC/DSW clock or the system clock.

Disk drive with servo system with timing adjustments to master timer for SAM detection errors

A 'write-squeeze-verify' method is used for verification of the data that has been written in the annular bands of a shingled magnetic recording disk drive. The writing of data along a track overwrites a portion of the previously written track and thus 'squeezes' the data of the previously written track to thereby form a &#x201c;shingled data track&#x201d; (SDT). The data in each SDT is read back and verified by an error correction check using error correction bits associated with the data written in the SDT, or by comparing the readback data with the data stored in memory. If the data read back is not verified, a write error counter is incremented and a write error frequency is calculated. One or more attempts to write the data can be performed. If the data in the SDT cannot be verified after the attempted rewrite(s), then a &#x201c;re-try fail&#x201d; is reported.

Shingled magnetic recording (SMR) disk drive with verification of written data

A method and system are described for performing an arithmetic operation such as multiplication or division of a fixed point variable measured at runtime by a floating point constant known at compile-time. The floating point constant is converted into a mantissa and a base-2 exponent at compile-time. The mantissa and exponent are preferably combined into a single unit (a word) of memory. At runtime either single multiplication and accumulation or matrix multiplication and accumulation is preferably achieved by a microprocessor or DSP instruction designed to use the mantissa-exponent pairs stored in a word of memory. The microprocessor instruction multiplies a fixed point runtime variable x by the mantissa and the result is shifted to the right or left as indicated by the exponent, which is preferably a 2's complement number. The complete instruction sequence to perform the multiplication can be made reentrant and can be pipelined.

Method and system for performing calculations using fixed point microprocessor hardware

A method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations are disclosed. An instruction is generated for shifting an operand to either maximum or the minimum value depending on the bit of data input when saturation occurs. A saturation detection circuit is combined with an arithmetic shifter and a final decision multiplexor. The final decision multiplexor receives the output from the arithmetic shifter and the saturated value from the saturation circuit. When saturation is detected by the saturation detection circuit, the final decision multiplexor selects the saturate minimum or the saturate maximum depending on whether the MSB of the data in equals one or zero, respectively.

Method, apparatus and program storage device that provides a shift process with saturation for digital signal processor operations

Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Decoding error correction codes using a modular single recursion implementation

A digital filter instruction and filter implementing the filter instruction are disclosed. The filter instruction synthesizes a digital filter and includes an instruction field, a tap length field, a coefficient address field, a data header address field, a clear accumulator bit and an update bit. The filter instruction a concise instruction format to significantly decrease memory required, allow for instruction pipelining without branch penalty, and uses a circular buffer for the data so the data address pointer is only needed to be updated for the next input sample. The filter instruction may be used to implement FIR or IIR filters by using the options of pre-clear accumulator or pre/post storing accumulator results.

Digital filter instruction and filter implementing the filter instruction

A magnetic disk for a hard disk drive comprising a plurality of physical sector sizes is disclosed. The magnetic disk includes a first sector size area physically formatted according to a first physical sector size and a second sector size area physically formatted according to a second physical sector size different from the first sector size by a multiple of the first sector size wherein the second sector size can be presented externally as multiple sectors of said first sector size.

Mixed format disk drive

Techniques are provided for performing Galois field arithmetic to detect errors in digital data stored on disks. Two 12-bit numbers or two 10-bit numbers are multiplied together in Galois field using tower arithmetic. In the 12-bit embodiment, a base field GF(2) is first extended to GF(2), GF(2) is extended to a first quadratic extension GF(2), and GF(2) is extended to a second quadratic extension GF(2). In the 10-bit embodiment, the base field GF(2) is first extended to GF(2), and GF(2) is extended to a quadratic extension GF(2). Each of the extensions for the 10-bit and 12-bit embodiments is performed using an irreducible polynomial. All of the polynomials used to generate the first and the second quadratic extensions of the Galois field are in the form x+x+K, where K is an element of the ground field whose absolute trace equals 1.

Techniques for performing reduced complexity galois field arithmetic for correcting errors

A combined encoder/syndrome generator is provided that has a reduced delay. The combined encoder/syndrome generator generates check symbols during an encoding process and error syndromes during a decoding process. The combined encoder/syndrome generator has two or more blocks. The output of each block is fed as an input into a subsequent block. Each block can perform computations in parallel to reduce the delay of the encoding system.

Combined encoder/syndrome generator with reduced delay

A method and apparatus for providing a processor based nested form polynomial engine are disclosed. A concise instruction format is provided to significantly decrease memory required and allow for instruction pipelining without branch penalty using a nested form polynomial engine. The instruction causing a processor to set coefficient and data address pointers for evaluating a polynomial, to load loading a coefficient and data operand into a coefficient register and a data register, respectively, to multiply the contents of the coefficient register and data register to produce a product, to add a next coefficient operand to the product to produce a sum, to provide the sum to an accumulator and to repeat the loading, multiplying, adding and providing until evaluation of the polynomial is complete.

Method and apparatus for providing a processor based nested form polynomial engine

Systems and methods are provided for performing error correction decoding. The coefficients of the error locator polynomial are iteratively determined for each codeword using a modular implementation of a single recursion key-equation solver algorithm. According to this implementation, a plurality of modules are used to calculate the current and previous coefficients of the error locator polynomial. One module is used for each correctable error. The modular single recursion implementation is programmable, because the number of modules can be easily changed to correct any number of correctable errors. Galois field tower arithmetic can be used to calculate the inverse of an error term. Galois field tower arithmetic greatly reduces the size of the inversion unit. The latency time can be reduced by placing the computations of the inverse error term outside the critical path of the error locator polynomial algorithm.

Growing community of inventors

Palo Alto, CA, United States of America

Kirk Hwang