International Business Machines Corporation

Kirk Edward Morrow

Robert Christopher Dixon

Hien Le

Phil C F Paone

Charles Ray Johns

James Xenidis

Glen Arthur Wiedemeier

John Cummings Schiff

Yoanna Baumgartner

Parag Birmiwal

Jethro C Law

Michael J Neuling

William Paul Hovis

Sundeep Chadha

Richard Nicholas

Richard Nicholas Iachetta, Jr

Maureen Terese Davis

Joseph D Gerwels

Systems, methods, and computer program products retrieve data from a low retrieval speed device. A request is made to retrieve data from the low retrieval speed device. A determination is made that the time to respond to the request will exceed a threshold amount of time. In response to the determination that the time to respond to the request will exceed the threshold amount of time, a load stall interrupt is generated. In response to the load stall interrupt, one or more system resources associated with a source of the request are released.

Load stall interrupt

A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Design Structure for switching digital circuit clock net driver without losing clock pulses

Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

Importation of virtual signals into electronic test equipment to facilitate testing of an electronic component

System and method for switching digital circuit clock net driver without losing clock pulses

Securing an integrated circuit, including fabricating the integrated circuit to include a multiplicity of unblown efuses, at least one surrogate efuse that emulates a blown efuse, non-volatile data representing the blown state of the surrogate efuse, and security circuitry; and setting, by the security circuitry when power is first applied to the integrated circuit, a security state of the integrated circuit in dependence upon whether a sensed state of the surrogate efuse is equal to the blown state of the surrogate efuse.

Securing an integrated circuit

Securing an integrated circuit, including fabricating the integrated circuit so that the integrated circuit includes at least one efuse that is intended to be always blown during operation of the integrated circuit and the integrated circuit includes security circuitry capable of blowing the efuse and of performing other security related functions; blowing, by the security circuitry of the integrated circuit, the efuse when power is applied to the integrated circuit and prior to performing any other security related functions; and setting, by the security circuitry after blowing the efuse, a security state of the integrated circuit in dependence upon a sensed state of the efuse.

Electronic component validation testing is facilitated by a method, system and program product which allows the importation of virtual signals derived from simulation verification testing of the electronic component design into electronic test equipment employed during validation testing of the actual electronic component. The method includes: storing simulation data resulting from simulation testing of an electronic component's design; employing electronic test equipment to perform real-time testing of the actual electronic component and obtain real-time test signals therefor; automatically correlating the stored simulation data with the actual real-time test signals; and performing at least one of: overlaying and/or displaying the correlated simulation data as virtual signals with the real-time test signals; and employing a trigger event automatically ascertained from the stored simulation data and triggering the electronic test equipment based thereon, thereby automatically controlling real-time testing of the electronic component via the stored simulation data.

A method, an apparatus, and a computer program are provided for sequentially determining parity of stored data. Because of the inherent instabilities that exist in most memory arrays, data corruption can be a substantial problem. Parity checking and other techniques are typically employed to counteract the problem. However, with parity checking and other techniques, there are tradeoffs. Time required to perform the parity check, for example, can cause system latencies. Therefore, to reduce latencies, a trusted register can be included into a memory system to allow for immediate access to one piece of trusted data. By being able to read one piece of trusted data, the system can overlap the parity checking and delivery of a location of data with the reading of the next location of data from the memory array. Hence, a full cycle of latency can be eliminated without the reduction of the clock frequency.

Method and apparatus for a modified parity check

A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is being blown, the constant current is diverted away from the core to the eFuse and as the eFuse blows, the constant current is again dumped to the semiconductor core. Thus, a change in current due to the transient of the eFuse being blown is not detectable and the information that an eFuse has been blown is kept secure.

Method and apparatus for protecting eFuse information

A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.

Method and apparatus for implementing power-saving sleep mode in design with multiple clock domains

The invention presents a method for selecting test cases in a test simulation of logic designs to improve speed and effectiveness of such testing. The method for selecting such test cases after such test cases are generated includes generating a test-coverage file and a harvest-goals file for the test case. The harvest-goals file contains a list of events and initial goal for each event. Harvest criteria is used to determined whether the number of hits for each event meets the initial goal. By applying the harvest criteria to the test case, it is determined whether to harvest the test case. The test case is saved and identified for harvest, if the test case is determined to be harvested. Also, the harvest-goals file is adjusted, if the test case is determined to be harvested.

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Round Rock, TX, United States of America

Kirk Edward Morrow