International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Sony Computer Entertainment Inc.

Toshiba America Electronic Components, Inc.

Kirk David Peterson

John J Ellis-Monaghan

Jeffrey P Gambino

Baozhen Li

Lawrence Alfred Clevenger

Jed Hickory Rankin

Junli Wang

John Edward Sheets, Ii

Mark David Jaffe

John B DeForge

Terence B Hook

Terry Allen Spooner

Alain F Loiseau

Andrew A Turner

Nathaniel R Chadwick

Chih-Chao Yang

Jerome Brett Lasky

Herbert Lei Ho

Babar Ali Khan

James William Adkisson

John Edward Barth, Jr

James A Culp

John Sheets

Cyril Cabral, Jr

Christian Lavoie

Robert Russell Robison

Robert J Purtell

Gilles Gervais

Donna Kaye Johnson

Yun Yu Wang

Charles W Koburger, Iii

David William Boerstler

Todd Alan Christensen

Saravanan Sethuraman

Xiao Hu Liu

William Paul Hovis

Diyanesh B Chinnakkonda Vidyapoornachary

Randy William Mann

Jieming Qi

Eskinder Hailu

Jason D Hibbeler

Norman Jay Rohrer

William Joseph Murphy

Mack Wayne Riley

Paul David Agnello

Todd Jon Rosedahl

Roy Arthur Carruthers

Peter James Lindgren

Ronnen Andrew Roy

Sridhar H Rangarajan

James McKell Edwin Harper

Marc Waine Cantell

Nicolas E Pizzuti

Mark A DiRocco

Mary Conroy Bushey

Theresa Newton

Zachary Henderson

Nicholas Palmer

Frances S M Clougherty

David Paul Agnello

Jean Louise Jordan-Sweet

Edward J Nowak

Brent A Anderson

Effendi Leobandung

Warren Edward Maule

Daniel Mark Dreps

Sang Hoo Dhong

Brian William Thompto

Karthick Rajamani

JunJun Li

Michael Stephen Floyd

David Paul Paulsen

Thomas M Shaw

Jon Alfred Casey

Charles Robert Lefurgy

Malcolm Scott Allen-Ware

James Spiros Nakos

Travis Reynold Hebig

Anthony Gus Aipperspach

Thomas Anthony Wassick

Chad Allen Adams

Steven Paul Ostrander

Gregory Scott Still

Srinivasan Ramani

Sungjun Chun

Jeffrey Douglas Brown

Victor V Zyuban

Brian W Quinlan

James Allan Bruce

Jonathan Daniel Chapple-Sokol

John Anthony Bracchitta

Charles L Reynolds

Cathryn Jeanne Christiansen

Norman Whitelaw Robson

Ezra D B Hall

Michael James Lercel

Tina Jane Wagner

David M Onsongo

Sylvain Pharand

Joshua D Friedrich

Multicomponent module assembly by identifying a failed site on a laminate comprising a plurality of sites, adding a machine discernible mark associated with the failed site, placing an electrically good element at a successful site; and providing an MCM comprising the laminate, and the electrically good element.

Multicomponent module design and fabrication

Data relating to one or more circuit paths may be collected during a design stage of a processor chip based on a design model. One or more delta values may be added to the one or more circuit paths of the design model. One or more broken circuit paths may be identified based on the one or more delta values. A target time for each of the one or more broken circuit paths may be adjusted.

Processor chip timing adjustment enhancement

A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.

Long channel and short channel vertical FET co-integration for vertical FET VTFET

A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Contacts having a geometry to reduce resistance

A system may include an integrated circuit having repair select bits coupled with a central repair register. The repair register may be configured to determine how to broadcast multiple repair actions to a group of repairable circuits. Inclusion of the repair register may function to reduce the total number of latches used to hold repair information.

Microchip level shared array repair

Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

Predetermining separate thermal control points for chips of a multi-chip module

A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

Enhancement of iso-via reliability

Embodiments are directed to a method for repairing features of a host semiconductor wafer. The method includes forming a feature of the host semiconductor wafer, wherein the feature includes a first conductive material and a surface having a planar region and non-planar regions. The method further includes forming a metal conductive liner over the non-planar regions. The method further includes applying a second conductive material metal layer over said the conductive liner. The method further includes recessing the second conductive material to be substantially planar with the planar region.

Metalization repair in semiconductor wafers

A method and performance-screen ring oscillator (PSRO) test structure for designing, testing, and manufacturing a VLSI device. The performance-screen ring oscillator (PSRO) test structure comprises a ring oscillator having a plurality of stages; one or more selectable loads, each selectable load being coupled to an output of a corresponding one of the stages of the ring oscillator; and one or more multiplexers, each multiplexer being coupled to at least one stage of the ring oscillator and being configured to select a configuration of the corresponding selectable load.

Performance-screen ring oscillator with switchable features

A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Semiconductor via structure with lower electrical resistance

Embodiments of the invention are directed to a method and resulting structures for identifying an integrated circuit (IC) chip using optically-unique features. In a non-limiting embodiment of the invention, an imaging device generates an image of the chip. One or more optical features of the chip within the image can be determined and stored in a local or remote database. Metadata associated with the chip can be generated and linked with the one or more optical features of the chip and a unique identifier of the chip in the database.

Passive methods of loose die identification

After printing common features from a primary mask into a photoresist layer located over a substrate, a functional feature which is suitable for changing functionalities or the configurations of the common features according to a chip design is selected from a library of additional functional features in a secondary mask. The selected functional feature from the secondary mask is printed into the photoresist layer to modify the common features that already exist in the photoresist layer. The selection and printing of functional feature processes can be repeated until a final image corresponding to the chip design is obtained in the photoresist layer.

Method and structures for personalizing lithography

Growing community of inventors

Jericho, VT, United States of America

Kirk David Peterson