International Business Machines Corporation

Kirk David Lamb

Kevin Charles Gower

Dustin James VanStee

Thomas J Griffin

Timothy John Slegel

Paul William Coteus

Markus Helms

Thomas Schlipf

Nihad Hadzic

Edward N Cohen

Rolf Fritz

Manfred Walz

Steven J Hnatko

Thomas Buechner

Charlotte Anne Reed

Donald H Friedberg

A computer-implemented method for generating one or more random numbers includes configuring a mapper to feed inputs of a random number generation system using a subset of noise sources from multiple noise sources. The random number generation system generates a random number based on the inputs. The method further includes evaluating the subset of noise sources and detecting that a first noise source from the subset of noise sources has degraded in quality. The method further includes evaluating a second noise source from the available noise sources, the second noise source not being in the subset of noise sources. In response to the second noise source satisfying a predetermined threshold criterion, the first noise source is replaced with the second in the subset of noise sources for providing random bit streams to facilitate generating the random number by the random number generation system.

Real time configuration of multiple true random number generator sources for optimized entropy generation

Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer program product for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a transfer logic used in a power-loss save of the write cache. The one or more operating parameters include an instance-specific process speed of the transfer logic which is retrieved as bin data. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Sizing a write cache buffer based on emergency data save parameters

Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency data save procedure. A computer implemented method for allocating a write cache on a storage controller includes retrieving, at run-time by a processor, one or more operating parameters of a component used in a power-loss save of the write cache. The component is selected from the group consisting of an energy storage element, a non-volatile memory, and a transfer logic. A size for the write cache on the storage controller is determined, based on the one or more operating parameters. A write cache, of the determined size, is allocated from a volatile memory coupled to the storage controller.

Soft error modeling of circuits. Soft error upset (SEU) specification and design information is received from a design entry. The SEU specification comprises expected SEU behavior of a node. A logical simulation model is created based on the SEU specification and the design information. A logical verification is performed based on the logical simulation model to produce a first result. The logical verification comprises selecting a first node for injection, injecting an SEU into the first node to produce a first result, and responsive to the first result not agreeing with the SEU specification, providing the first result to the design entry. A netlist based on the SEU specification and the design information is created. The netlist comprises a specification-based-logic-derating derived from the SEU specification. A physical design verification based on the netlist, a logic derating, and clock information is performed. It comprises calculating node failure-in-time based on the specification-based-logic-derating.

Modeling for soft error specification

The present invention is directed to margin characterization of memory devices, such as interface ASICs connected to SDRAM. The circuits and method perform margin characterization on a chip during wafer test; however the characterization could also be performed at module test or in a system.

SMI memory read data capture margin characterization circuits and methods

A system and method for providing SDRAM mode register shadowing in a memory system. A system includes a memory interface device adapted for use in a memory system. The memory interface device includes an interface to one or more ranks of memory devices, and each memory device includes one or more types of mode registers. The memory interface device also includes an interface to a memory bus for receiving commands from a memory controller. The commands include a mode register set command specifying a new mode register setting for one or more ranks of memory devices and a mode register type. The memory interface device further includes a mode register shadow module to capture settings applied to the mode registers. The module includes a shadow register for each type of mode register and a shadow log for each type of mode register. The module also includes mode register shadow logic to detect a mode register set command, to store the new mode register setting in the shadow register corresponding to the specified mode register type, and to set one or more bits in the shadow log corresponding to the specified mode register type to indicate which of the ranks of memory devices have been programmed with the new mode register setting.

System and method for providing synchronous dynamic random access memory (SDRAM) mode register shadowing in a memory system

A synchronous input to output protocol translator supporting multiple reference oscillator frequencies and fixed latency data computation and chip crossing circuits enables implementation of a method for delaying oscrelative to oscin a configurable way to provide a constant, minimal Tover a range of refosc frequencies between circuits for data transferred. It requires that the data transferred from a register Rbe sent over multiple wires via configurable delay circuitry for osc, capture circuitry at the input to R, and a circuit to transfer a synchronizing signal from a non-delayed clock domain to a delayed clock domain. Relative to osc, oscis a delayed, synchronous clock.

Fixed latency data computation and chip crossing circuits and methods for synchronous input to output protocol translator supporting multiple reference oscillator frequencies

A non-obtrusive activity monitor is proposed for advantageously monitoring and tracing disjunct, concurrent computer system operations in heavily queued computer systems. For each traced and pending computer system operation, the monitor uses a hardware implementation of an event triggered operation graph to trace the path of the computer system operation through the computer system. For each followed path, a unique signature is generated that significantly reduces the amount of trace data to be stored. In a preferred embodiment, the trace information is stored together with a time stamp for debugging and measuring queuing effects and timing behavior in a computer system.

Operation graph based event monitoring system

A memory interface device uses a driver impedance adjustment engine with state machine for off chip driver (OCD) calibration which is used to set the driver voltage levels of the DRAM memory module or DIMM of the JEDEC DDR-II standard type. By adjusting the pull-up drive strength and pull-down drive strength, the output voltage levels and the rise times can be optimized to find the minimal signal swing that is still immune to noise, while not degrading the data eye significantly. The state machine finds the optimal setting for the DRAM Driver Impedance, using both DC and AC methods adjusting the value of the driver impedance through a master ASIC, and then sampling the known value sent back from the DRAM. The state machine will stop when the optimal value of the driver impedance is found and automates the process of detecting the optimal driver impedance and configuring the DRAM module or DIMM accordingly. The ASIC circuit and method use a data strobe, not only as strobe, but as data input during OCD calibration. Optimal driver impedance setting of a DDR-II DRAM is detected in a DC mode. Using AC-BIST the optimal driver impedance setting can be adjusted and optimized to account for AC timing influences such as coupled noise, data dependent jitter, and intersymbol interference.

DDR-II driver impedance adjustment control algorithm and interface circuits

A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref&equals;1/m*Vddq&plus;OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n&minus;1/n*Vddq, where n is the voltage granularity of the DAC.

Alternating current built in self test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test

A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref&equals;1/m*Vddq&plus;OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n&minus;1/n*Vddq, where n is the voltage granularity of the DAC.

Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem

A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of Memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref&equals;1/m*Vddq&plus;OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n * Vddq to n&minus;1/n*Vddq, where n is the voltage granularity of the DAC.

DIGITAL-TO-ANALOG CONVERTER (DAC) FOR DYNAMIC ADJUSTMENT OF OFF-CHIP DRIVER PULL-UP AND PULL DOWN IMPEDANCE BY PROVIDING A VARIABLE REFERENCE VOLTAGE TO HIGH FREQUENCY RECEIVER AND DRIVER CIRCUITS FOR COMMERCIAL MEMORY

A memory subsystem package has a memory controller interface ASIC (application specific integrated circuit) and a plurality of memory modules. The ASIC has a bi-directional serial protocol i2C communication bus to off chip drivers for monitoring temperature and for adjusting the environment surrounding the package by controlling fans using fan switches and variable voltage controls. In addition there is provided an Alternating Current Built in Self Test (AC. BIST) with variable data receiver voltage reference for performing high-speed AC memory subsystem self-test for that ASIC enabling writing of pseudo-random patterns to memory, reading them back and comparing the expected results at hardware speeds. Vref can be made to vary across its allowable range during AC self test to provide improved coverage. The system monitors Vddq during normal system operation using an ADC. The system varies Vref as a function of Vddq, using a combination of a DAC and ADC. The system varies Vref as a function of Vddq, such that Vref&equals;1/m*Vddq&plus;OFFSET, where m can be 1, 2, 4, or 8, and where OFFSET can be positive or negative ranging from 1/n*Vddq to n&minus;1/n*Vddq, where n is the voltage granularity of the DAC.

Analog-to-digital converter for monitoring VDDQ and dynamically updating programmable Vref when using high-frequency receiver and driver circuits for commercial memory

A time-division multiplex system is disclosed where the data from two sources is coupled over a multiplexer controller by a generator comprising an XOR gate and a pair of latches where the output of both latches are coupled to the XOR gate and an inverter at the input of each latch. One of the latches is gated by a master clock signal and the other latch is gated by a clocked signal skewed approximately one-half clock cycle.

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Kingston, NY, United States of America

Kirk David Lamb