Micron Technology Incorporated

Round Rock Research, LLC

Micron Semiconductor, Inc.

Micro Technology, Inc.

Other

Kirk D Prall

Durai Vishak Nirmal Ramaswamy

Guy T Blalock

Gurtej S Sandhu

Chun Chen

Werner Juengling

Sujit Sharan

Pai-Hung Pan

Howard E Rhodes

Tyler A Lowrey

Trung Tri Doan

Aftab A Ahmad

Haitao Liu

Kamal M Karda

Mike P Violette

Leonard Forbes

Fernando N Gonzalez

Pierre C Fazan

Zengtao T Liu

Ravi T Iyer

Alan R Reinberg

Gordon A Haller

Wayne I Kinney

Ashonita A Chavan

Qian Tao

Seiichi Aritome

Randhir P Thakur

Philip J Ireland

Behnam Moradi

Di Li

Chris Larsen

Ferdinando Bedeschi

Mark Alan Helm

Michael A Smith

Andrei Mihnea

Alessandro Calderoni

Randhir P S Thakur

Zhiqiang (Jeff) Wu

Graham Richard Wolstenholme

D Mark Durcan

Paul S Zagar

Robert B Kerr

Christopher Murphy

Tod S Stone

Scott E Sills

Arup Bhattacharyya

Luan C Tran

Scott G Meikle

Kevin J Ryan

David J Keller

Ramanathan Gandhi

Kenneth N Hagen

Robert Quinn

Gurtel Sandhu

Sanh D Tang

Kevin G Donohoe

Roger W Lindsay

Mitsunari Sukekawa

David S Becker

Sukesh Sandhu

Sung C Kim

Lyle Jones

David L Dickerson

David H Wells

Thomas Arthur Figura

Albert Fayrushin

Zhigiang (Jeff) Wu

Brett Rolfson

Gregg Rettschlag

Nirmal Ramaswamy

A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors

The hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

Hybrid memory device using different types of capacitors

A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.

Semiconductor devices comprising transistors having increased threshold voltage and related methods and systems

A method of forming an array of capacitors comprises forming a vertical stack above a substrate. The stack comprises a horizontally-elongated conductive structure and an insulator material directly above the conductive structure. Horizontally-spaced openings are formed in the insulator material to the conductive structure. An upwardly-open container-shaped bottom capacitor electrode is formed in individual of the openings. The bottom capacitor electrode is directly against conductive material of the conductive structure. The conductive structure directly electrically couples the bottom capacitor electrodes together. A capacitor insulator is formed in the openings laterally-inward of the bottom capacitor electrodes. A top capacitor electrode is formed in individual of the openings laterally-inward of the capacitor insulator. The top capacitor electrodes are not directly electrically coupled together. Structure independent of method is disclosed.

Array of capacitors, an array of memory cells, a method of forming an array of capacitors, and a method of forming an array of memory cells

A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

Memory cells

Some embodiments include a semiconductor construction having a gate extending into a semiconductor base. Conductively-doped source and drain regions are within the base adjacent the gate. A gate dielectric has a first segment between the source region and the gate, a second segment between the drain region and the gate, and a third segment between the first and second segments. At least a portion of the gate dielectric comprises ferroelectric material. In some embodiments the ferroelectric material is within each of the first, second and third segments. In some embodiments, the ferroelectric material is within the first segment or the third segment. In some embodiments, a transistor has a gate, a source region and a drain region; and has a channel region between the source and drain regions. The transistor has a gate dielectric which contains ferroelectric material between the source region and the gate.

Transistors, memory cells and semiconductor constructions

The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Cross-point memory compensation

Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

Memory cell imprint avoidance

A hybrid memory device may include volatile and non-volatile memory cells on a single substrate, or die. The non-volatile memory cells may have ferroelectric capacitors and the volatile memory cells may have paraelectric or linear dielectric capacitors for their respective logic storage components. In some examples, the volatile memory cells may be used as a cache for the non-volatile memory cells. Or the non-volatile memory cells may be used as a back-up for the volatile memory cells. By placing both types of cells on a single die, rather than separate dies, various performance metrics may be improved, including those related to power consumption and operation speed.

Hybrid memory device using different types of capacitors and operating method thereof

Some embodiments include an assembly having a memory cell with an active region which includes a body region between a pair of source/drain regions. A charge-storage material is adjacent to the body region. A conductive gate is adjacent to the charge-storage material. A hole-recharge arrangement is configured to replenish holes within the body region during injection of holes from the body region to the charge-storage material. The hole-recharge arrangement includes a heterostructure active region having at least one source/drain region of a different composition than the body region, and/or includes an extension coupling the body region with a hole-reservoir. A wordline is coupled with the conductive gate. A first comparative digit line is coupled with one of the source/drain regions, and a second comparative digit line is coupled with the other of the source/drain regions.

Integrated memory having the body region comprising a different semiconductor composition than the source/drain region

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Boise, ID, United States of America

Kirk D Prall