International Business Machines Corporation

Micron Technology Incorporated

Kirk D Pospesel

Michael Grassi

Raymond Michael Higgs

Howard M Haynie

Clinton E Bubb

Luke M Hopkins

Gabriel Martel Tarr

Tony M Brewer

Douglas James Joseph

Philip Jacob

Marcel Schaal

James P Coghlan

Dean A Liberty

Steven George Aden

Thomas F Dubois

Devices and techniques for packet arbitration for buffered packets in a network device are described herein. A packet can be received at an input of the network device. The packet can be placed in a buffer for the input and a characteristic of the packet can be obtained. A record for the packet, that includes the characteristic, is written into a data structure that is independent of the buffer. Arbitration, based on the characteristic of the packet in the record, can then be performed among multiple packets to select a next packet from the buffer for delivery to an output.

Packet arbitration for buffered packets in a network device

A device allocates buffer space for storing data received from another device. The other device has a credit balance corresponding to the amount of buffer space. A sending device reduces its number of credits by a cost of a packet and sends the packet. To ensure that the buffer does not overflow, the sending device spends a credit for each entry in the buffer that could be consumed by the sent data packet. When received data is added to the buffer without consuming a new entry, a response packet that returns a credit is sent to the sending device before the data is read from the buffer. Thus, the sending device is enabled to continue sending data without waiting for the buffer to be read, enabling the communication between the two devices to make more efficient use of the buffer.

Early credit return for credit-based flow control

A computer implemented method and system for managing power in a 3D chip stack formed of multiple memory layers each having a plurality memory banks and a plurality of Through-Silicon-Vias (TSVs) connecting the memory banks. The TSVs are arranged in a plurality of subsets, each subset of TSVs connecting a corresponding vertical stack of memory banks aligned across a plurality of memory layers. The method includes determining a power delivery budget for each subset of TSVs connecting the corresponding vertical stack of memory banks based on memory requests, keeping track of memory requests to the memory banks of each vertical stack of memory banks and scheduling the memory requests to the memory banks of each vertical stack of memory banks based on the power budget. The memory controller is configured with a scorecard scheduler to manage the memory requests based on the power budget.

Power aware scheduling of requests in 3D chip stack

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Configurable hardware queue management and address translation

A system for managing one or more queues in a multi-processor environment includes a memory configured to be accessed by a plurality of processing elements, and a queue manager disposed in communication with a plurality of processors and with the memory, the queue manager configured to control a queue in the memory, the queue including a plurality of queue elements, the queue manager configured to intercept a message from a processing element of the plurality of processing elements and perform one or more queuing operations on the queue based on the message. The system also includes a dynamically configurable queue full value maintained by the queue manager, the queue full value being a threshold value that specifies a maximum number of the queue elements that can be written to before a queue full condition is detected, the maximum number based on a number of processing elements.

Hardware queue manager with water marking

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Configurable hardware queue management

A method, an apparatus and computer readable medium for simultaneous communication over a bus in a master/slave agent network topology. Each communication agent on the network is either a master agent or slave agent with an input and an output. In one embodiment, the input and the output are latches. The method permits the number of tokens on the ring to be equal to up to one less than the total number of agents on the ring.

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Palenville, NY, United States of America

Kirk D Pospesel