Texas Instruments Corporation

Drs Network & Imaging Systems, LLC

Drs Rsta, Inc.

Drs Technologies, Inc.

Kirk D Peterson

Dana Dudley

George Dee Skidmore

Kevin N Sweetser

Eugene E Krueger

Cari A Ossenfort

Daniel B Jardine

Charles M Hanson

Qunying Li

Eric G Soenen

Congzhong Huang

Mark V Wadsworth

Fredrick W Trafton

James E Nave

Andrew J Cringean

James R Craig

Methods and structures of photodetectors are described. The structure may include a readout integrated circuit substrate having an internally integrated capacitor. The structure may additionally include an external capacitor overlying the readout integrated circuit substrate. The external capacitor may be coupled with the internally integrated capacitor of the readout integrated circuit substrate, and configured to operate in parallel with the internally integrated capacitor of the readout integrated circuit substrate. The structure may also include a detector overlying the external capacitor.

High density capacitor integrated into focal plane array processing flow

One embodiment of the invention includes a regulator system that includes a high-side power transistor electrically connected between a first node and a second node. The system also includes a low-side power transistor electrically connected between the second node and a third node. The high and low-side power transistors can be controlled by high and low-side control signals, respectively. A mode controller provides at least one mode control signal having a value to enable operation of the regulator system in each of a buck switching, boost switching, negative switching, and linear regulator mode. The regulator system can utilize at least one of the high-side power transistor and the low-side power transistor to operate in the selected mode depending on at least one of an input voltage and an arrangement of external circuitry that are electrically coupled to at least one of the first, second, and third nodes to provide a regulated output voltage.

Reconfigurable regulator and associated method

The present invention includes a plurality of FETs () including an operational amplifier with additional FETs () arranged as current mirrors, and a sense FET (), and a current sensed at FET () is amplified, compared to a reference signal, the difference current derived from the amplified sense current and reference signal being amplified and provided at an output for use in control applications.

Current sensing circuit and method

A system and method is provided for monitoring a voltage level of a charge pump device. The system and method employ a first charging device that is coupled to an output of a charge pump through a switching system. The first charging device is then decoupled from the output of the charge pump device and coupled to a second charging device. The charge on the first charging device is then redistributed between the first charging device and the second charging device. The output of the second charging device is a reduced voltage (e.g., below 5 volts) based on the ratio of the charge distribution between the first and second charging devices. The output of the second charging device can then be compared to a reference voltage to determine if the voltage of the charge pump device is at an adequate voltage level.

Charge pump with switched capacitor feedback

The speed performance of a resistive DAC can be improved by tailoring the selection switch size to the node location. For the simple case of a DAC used in a SAR-based ADC, the MSB code, which is activated during each SAR search, is the speed-limiting bit. Increasing the size of the switch on the node corresponding to the MSB will reduce the on-resistance of the FET and, therefore, the total resistance to ground from the node. The on-resistance can be changed markedly without substantially changing the total capacitance at the output node, since the sum of the parasitic from the remaining switches will far exceed the additional capacitance created by increasing the MSB FET.

Resistor string DAC with improved speed

This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is a band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.

Focal plane array integrated circuit with individual pixel signal

An integrated analog to digital interface subsystem for imaging applications includes digital global and digital pixel by pixel offset correction and scaling. The integrated interface 2 includes 3 DAC's 2c1-2c3 that are used to do a rough offset cancellation on the three analog input signals (RGB) in the analog domain. A triple sample/hold circuit 2a samples the RGB signals simultaneously, multiplexes the data and passes the three signals on the ADC 2b sequentially (at about 3 times the data rate). The sample/hold circuit 2a has the capability to operate in fully differential as well as single ended input mode, and can perform correlated double sampling if needed. A high resolution ADC 2b converts the 3 multiplexed signals from simple/hold circuit 2a. A first digital offset correction circuit 2f restores the level of the RGB signals in the digital domain on a pixel by pixel basis. A first digital gain correction circuit 2g compensates for sensitivity variations of the RGB sensors in the digital domain on a pixel by pixel basis. A second digital offset correction circuit 2h restores the overall DC level of the RGB signals in the digital domain. A second digital gain correction circuit 2i compensates for overall sensitivity variations of the RGB sensors in the digital domain. A serial interface 2d is used to load the overall gain and offset coefficients.

Analog to digital video converter

This is a monolithic infrared detector readout circuit for a capacitive sensing element 111 wherein a high gain preamplifier 115 is biased by a large bias element 113, e.g. on the order of 10.sup.12 ohms. The output of the preamplifier 115 is band-limited by a low pass single-pole filter 117 having a high value resistive element 119, e.g. on the order of 10.sup.9 ohms, and then is clamped by a clamp circuit 131 to a stable reference in a manner that doubles the amplitude of the signal and minimizes low frequency bias shifts and fixed pattern noise. The output of the clamp circuit 131 is buffered by buffer 123 prior to being multiplexed by row address signals. The output from a multiplex switch 125 is then applied to the column line for output to a video circuit or the like.

A current mirror circuit (40) includes a first pair of mirrored transistors (T.sub.1 and T.sub.2) having common gate and source connections; a second pair of cascoded transistors (T.sub.3 and T.sub.4) with common gate connections, respectively connected in series between the first pair transistors (T.sub.1 and T.sub.2) and input and output voltage terminals (+V.sub.IN and +V.sub.OUT). First and second voltage level shifter circuitries (41,42) establish shifted bias voltages respectively at the first and second pair transistor gate connections. The first voltage level shifter comprises a pair of transistors (T.sub.5 and T.sub.6) connected in series between an applied voltage terminal and the second pair transistor source connections, for establishing a shifted biasing voltage at the second pair transistor gate connection. The second voltage level shifter comprises a pair of transistors (T.sub.7 and T.sub.9) connected in series between the applied voltage terminal and the first pair transistor source connections, for establishing a bias voltage at the first pair transistor gate connections.

Dual voltage level shifted, cascoded current mirror

A current mirror circuit (40) includes a first pair of mirrored transistors (T.sub.1 and T.sub.2) having common gate and source connections; a second pair of cascoded transistors (T.sub.3 and T.sub.4) with common gate connections, respectively connected in series between the first pair transistors (T.sub.1 and T.sub.2) and input and output voltage terminals (+V.sub.IN and +V.sub.OUT). First and second voltage level shifter circuitries (41,42) establish shifted bias voltages respectively at the first and second pair transistor gate connections. The first voltage level shifter comprises a pair of transistors (T.sub.5 and T.sub.6) connected in series between an applied voltage terminal and the second pair transistor source connections, for establishing a shifted biasing voltage at the second pair transistor gate connection. The second voltage level shifter comprises a pair of transistors (T.sub.7 and T.sub.8) connected in series between the applied voltage terminal and the first pair transistor source connections, for establishing a bias voltage at the first pair transistor gate connections.

A monolithic infrared detector readout circuit for a capacitive detection element wherein a high gain preamplifier is biased by a large amplifier feedback resistance, on the order of 10.sup.12 ohms. The output of the preamplifier is bandlimited by a low pass single-pole filter having a high value resistor on the order of 10.sup.9 ohms and then is buffered prior to being multiplexed by row address signals. The output from the multiplexer switch is then applied to the column line for output to a video circuit or the like.

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Plano, TX, United States of America

Kirk D Peterson