Cirrus Logic Inc.

Kirit B Patel

Michael E Runas

G R Rao

A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Digital step generators and circuits, systems and methods using the same

Systems and methods for testing ASIC and RAM memory devices are disclosed. The method comprises determining a signature map of valid power supply current values for a known good microcircuit wherein each valid power supply current value is measured at a fixed level of power supply voltage and corresponds to a unique test input stimuli pattern applied to the known good microcircuit. The signature map of power supply current values is stored in an electronic memory (300). The test input stimuli patterns are then applied to an unproven microcircuit (330) and the power supply current of the unproven microcircuit is forced to the levels stored in the signature map by a current supply (360) while the voltages across the power supply inputs of the unproven microcircuit are measured by a voltmeter (340). The measured power supply voltages for each power supply current value are then compared to the fixed voltage supply level used to test the known good microcircuit. The unproven microcircuit is faulted if any measured power supply voltage of the unproven microcircuit differs substantially from the fixed power supply voltage applied to the known good microcircuit.

Circuits, systems and methods for testing ASIC and RAM memory devices

Data transmission circuitry 200 is disclosed which includes a transmission line 201, driver circuitry 202, and receiver circuitry 206. Driver circuitry 202 is coupled to transmission line 201 and sets transmission line 201 to a low transmission voltage level during transmission of information of a first logic state and sets transmission line 201 to a higher transmission voltage during transmission of information of a second logic state. Receiver circuitry 206 compares the voltage on transmission line 201 with a static reference voltage which is a predetermined fraction of the higher transmission voltage and in response latches an output to a corresponding logic state. Receiver circuitry 206 latches the output in an output high logic state to an output voltage which is a multiple of the higher transmission voltage.

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Dallas, TX, United States of America

Kirit B Patel