Xilinx, Inc.

Kiran Puranik

Millind Mittal

Jaideep Dastidar

Ashish Gupta

Chuan Cheng Pan

Hanh Hoang

Siva Prasad Gadey

A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.

Logical transport over a fixed PCIE physical transport network

Embodiments herein describe a layer converter that includes a proxy legacy interface that permits the layers for a legacy interconnect protocol to be recycled without any modifications, thus achieving legacy functionality alongside the new protocols' layer implementation. Put differently, the layer converter permits the layers of the legacy interconnect protocol to be reused to permit data to be transmitted on a link shared with data transmitted using a new interconnect protocol.

Multiple protocol layer conversion

A scheduling system includes a request masking circuit configured to receive a plurality of original requests for priority arbitration among a plurality of entries, the plurality of original requests include a last original request and a first original request following the last original request. A last mask associated with a last grant result for the last original request is received from a mask generator circuit. A first masked request is generated by applying the last mask to the first original request. A request selection circuit is configured to generate a first selected request based on the first original request and the first masked request. The mask generator circuit is configured to generate a first mask based on the first selected request. The first mask is associated with a first grant result for the first original request.

System and method for round robin scheduling

A method for providing access by a virtual context to a physical instance includes receiving a request to access a physical instance of a plurality of physical instances of a hardware resource of a device. The request is associated with a virtual machine of a plurality of virtual machines. The method next determines that one of the physical instances is available, and assigns a virtual context associated with the virtual machine to access the one of the physical instances when the one of the physical instances is available. The assigning comprises retrieving the virtual context from a memory of the device and loading the virtual context into the one of the physical instances. The method then stores the virtual context in the memory after the one of the physical instances is accessed by the virtual context.

Caching virtual contexts for sharing of physical instances of a hardware resource

Approaches for configuring programmable resources of a programmable IC are disclosed. A first set of configuration data is loaded using a configuration port of the programmable IC, which also includes input/output (I/O) ports. Programmable resources are configured according to the first set of configuration data to implement a master data link circuit and at least one slave data link circuit. The master data link circuit includes a hardwired communication circuit, and a set of the programmable resources arranged to form a communication control circuit configured to control the communication circuit to provide a data link for communicating data via one of the I/O ports. A second set of configuration data is loaded using the master data link circuit. Programmable resources of the programmable IC are configured according to the second set of configuration data to implement a logic circuit configured to communicate data via the slave data link circuit.

Configuration of programmable integrated circuits

In one embodiment, a multi-protocol communication circuit is provided. The communication circuit includes a plurality of protocol bridge circuits, each configured to convert data between a first format and a respective second format corresponding to a respective communication protocol. A switch network provides routable connections between the protocol bridge circuits and one or more interface circuits. Each interface circuit is configured to convert data between the first format and a raw data format. Due to the common first format, an interface circuit may be configured for select ones of different communication protocols by routing data in the first format between the interface circuit and a protocol bridge circuit corresponding to the select one of the different communication protocols.

Multi-protocol data bus interface

An embodiment of a method for credit-based flow control is disclosed. For this embodiment of the method, a first transaction layer packet from a sending device is loaded into a receiver buffer of a receiving device. A second transaction layer packet is loaded into the receiver buffer, where the second transaction layer packet is of a different packet type than the first transaction layer packet. The first transaction layer packet is unloaded from the receiver buffer without return of a credit for the unloading of the first transaction layer packet from the receiver buffer. The first transaction layer packet is loaded into a side buffer, and the credit for the first transaction layer packet is sent to the sending device responsive to unloading or anticipated unloading of the first transaction layer packet from the side buffer.

Credit-based flow control

An integrated circuit ('IC') includes a peripheral component interconnect express ('PCIe') root complex having a central processing unit (&#x201c;CPU&#x201d;), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe endpoint device through a PCIe switch. The PCIe endpoint device is configured to initiate data transfer between the main memory and the PCIe endpoint device.

Direct memory access technique for use with PCIe endpoints

An integrated circuit ('IC') with a peripheral component interconnect express ('PCIe') has at least two data sinks () and a data source () capable of providing data packets to either data sink. A switch () of the PCIe system includes a first buffer () queuing data packets for one of the data sinks and a second buffer () queuing data packets for the other data sink. A status detector () detects when the first buffer equals or exceeds a selected buffer threshold, and a status-based flow control transmitter () sends a data link layer packet (&#x201c;DLLP&#x201d;) to the status-based flow control receiver () of the data source to cease transmitting first data packets while continuing to transmit second data packets.

Growing community of inventors

Fremont, CA, United States of America

Kiran Puranik