Freescale Semiconductor,inc.

Motorola Corporation

The University of Texas System

Nxp USA, Inc.

Synopsys, Inc.

Kiran Kumar Gullapalli

Steven D Hamm

Dean P Neikirk

Mayukh Bhattacharya

Kuntal Joardar

Kevin J Kerns

Brian J Mulvaney

Sergei G Rusakov

Sergei L Ulyanov

Mikhail M Zharov

Svetlana Rudnaya

Steven R Beckerich

Mark M Gourary

A method facilitates simulating a plurality of circuit elements connected to a multiport interconnect structure having a first set of ports. The method includes: receiving a first set of data that models electrical behavior of the first set of ports and a first portion of the plurality of circuit elements; determining a first subset of the first data, which models electrical behavior of a set of exposed ports of the first set of ports, and a second subset of the first data, which models electrical behavior of a set of non-exposed ports of the first set of ports and the first portion of the plurality of circuit elements; and combining the second subset of the first data into the first subset of the first data to generate a second set of data that models electrical behavior of a second interconnect structure having fewer ports than the multiport interconnect structure.

Method and apparatus to facilitate simulating a circuit connected to a multiport interconnect structure

A system and method of accelerating sparse matrix operations in full accuracy simulation of a circuit includes determining repetitive blocks of the circuit, determining a set of values of a current block, determining whether the state of the current block is sufficiently close to the state of a stored block solution when the corresponding values are within a predetermined error range, and performing a reduced computation using the stored block solution to provide a solution for the current block when the states are sufficiently close to each other. The reduced computation includes retrieving previously stored solutions and performing substantially simplified matrix and vector operations while maintaining accuracy of the solution. Reduced precision versions of the values may be used to generate a hash index used to store the block solutions. Stored redundant device information may also be used to simplify device solutions in a similar manner.

Method and apparatus for accelerating sparse matrix operations in full accuracy circuit simulation

A mechanism for improving speed of table model-based simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having substantially the same properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, a cache lookup is performed to determine table model solution values for the previously-evaluated transistor or device, and those values are used to determine exact output values per the table model of the presently being evaluated transistor or device.

Table model circuit simulation acceleration using model caching

A mechanism for improving speed of simulation of complex circuits that include transistors and other devices that share similar properties is provided. Circuit simulation speed is improved by efficiently identifying transistors and other devices having identical properties that share a same state at the time of interest in the simulation. Transistors and other devices are collected into groups having the same characteristics and topologies prior to simulation. Then during simulation, a determination is made as to whether a previously-evaluated transistor or device in the same group as a presently-being evaluated transistor or device has terminal input values that are the same, or nearly the same. If so, then output values of the previously-evaluated transistor or device are used in calculating the output values of the present transistor or device.

Circuit simulation acceleration using model caching

A method of providing simulation results includes detecting any power net and rail in a circuit netlist. The circuit can be divided into net-partitioned blocks. Using these net-partitioned blocks, a topological analysis can be performed to identify cuttable/un-cuttable devices and synchronization requirements. Then, the circuit can be re-divided into rail-partitioned blocks. Using these rail-partitioned blocks, a sparse solver can identify potential partitions, but eliminate fill-ins as determined by the topological analysis. A cost function can be applied to the potential partitions as well as the identified cuttable/un-cuttable devices to determine final cut points in the circuit and dynamic inputs to the final blocks. Simulation can be performed on the final blocks and simulation results can be generated.

Automatic, hierarchy-independent partitioning method for transistor-level circuit simulation

A circuit on an integrated circuit is made from a design that is verified using a design tool. The design tool takes a model of the circuit and generates equations with respect to nodes on the circuit. The time consuming task of completely determining the voltage at each node is performed for a predetermined input. To determine the node voltages for other signals, the first order transfer function of the equations is taken and then calculated for the predetermined input. A first order estimate of the node voltages is achieved using this first order transfer function and the node voltages determined from the predetermined input. A second order estimate is achieved using the first order transfer function and the first order estimate. A third order estimate is achieved using the first order transfer function and the second order estimate. The circuit design is verified for manufacturabiltity then manufactured.

Method and apparatus for distortion analysis in nonlinear circuits

The present invention relates generally to analyzing small signal response and noise in nonlinear circuits. One embodiment relates to a computer implemented method for analyzing an electrical circuit. The method includes receiving a circuit description and circuit element models, generating circuit equations using the circuit description and models, and determining a periodic stead-state response of the electrical circuit in the time domain. The method further includes linearizing the circuit element models about the steady-state response, generating a time-varying linear system of equations, and representing a small signal solution to the time-varying linear system of equations in response to a sine wave input as an amplitude modulated sine wave. The method also includes discretizing the time-varying linear system of equations by discretizing only the amplitude modulation of the small signal solution and performing a time-varying small signal analysis of the electrical circuit using the discretized equations.

Method and apparatus for analyzing small signal response and noise in nonlinear circuits

A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.

Method of simulating an integrated circuit

The present invention generates a model of a graded channel transistor having at least two channel portions of differing doping concentrations. The present invention assumes a uniform doping concentration of each channel portion. Each of the channel portions is modeled using a standard transistor model (100, 120) with junction voltages (64) resulting between the transistor models. The junction voltages (64) are determined to be at a level such that the channel currents of the transistor models (60, 62) are equal. Once the junction voltages (64) are determined, the parameters of the transistor models (60, 62) are determined. Once the transistor models (60, 62) are determined, the models are combined to produce a composite transistor model (70) for the transistor using standard circuit reduction techniques. The composite model produced is scalable with respect to geometry, is continuous, and is differentiable. Steps are also disclosed for manufacturing integrated circuits using the modeling techniques of the present invention.

Apparatus and method for modeling a graded channel transistor

Heterostructure barrier quantum well device with a super-lattice structure of alternating lightly doped and heavily doped spacer layers having multiple, stable current-voltage curves extending continuously through zero bias at ambient temperature. The device can be repetitively switched between the multiple current-voltage curves. Once placed on a particular curve, the device retains memory of the curve it has been set on, even if held at zero bias for extended periods of time. The device can be switched between current-voltage curve settings at higher positive or negative voltages and can be read at lower voltages. Switching between current-voltage curve settings can also be effected by additional terminal connection(s) to the spacer layer(s).

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Austin, TX, United States of America

Kiran Kumar Gullapalli