Apple Inc.

Kiran Kattel

Brijesh Tripathi

Erik P Machnicki

Robert E Jeter

Rakesh L Notani

Manu Gulati

Sukalpa Biswas

Shu-Yi Yu

Gilbert H Herbeck

Kai Lun Hsiung

Fabien S Faure

Venkata Ramana Malladi

Neeraj Parik

Shiva Kumar

Chaitanya Polapragada

Allen Kim

Charles Francis Dominguez

Jung Wook Cho

Eric G Smith

Bo Yang

Vijay M Bettada

Khaled M Alashmouny

Jim Jian Lin

Ashima Kapur

Wenlong Wei

An electronic device may include an applications processor that communicates with a peripheral input-output (I/O) device using a coprocessor. The applications processor may include a first interprocessor communications (IPC) module, whereas the coprocessor may include a second IPC module for interfacing with the first IPC module. The first IPC module may forward a group of transactions to a submission queue and may ring a submission doorbell interrupt to signal that work items are pending in the submission queue. In response, the second IPC module may dequeue the work items from the submission queue and process these items at the I/O device. The second IPC module may provide a group of completed transactions to a completion queue and may ring a completion doorbell interrupt to signal that items are pending in the completion queue. Thereafter, the completed items are forwarded to other parts of the applications processor for processing.

Methods for mitigating system interrupts for an electronic device

An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Reference voltage calibration using a qualified weighted average

In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

Timebase synchronization

An under voltage detection circuit and method of operating an IC including the same is disclosed. In one embodiment, an IC includes an under voltage protection circuit having first and second comparators configured to compare a supply voltage to first and second voltage thresholds, respectively, with the second voltage threshold being greater than the first. A logic circuit is coupled to receive signals from the first and second comparators. During operation in a high performance state by a corresponding functional circuit, the logic circuit is configured to cause assertion of a throttling signal responsive to an indication that the supply voltage has fallen below the first threshold. A clock signal provided to the functional circuit may be throttled responsive to the indication. If the supply voltage subsequently rises to a level above the second threshold, the throttling signal may be de-asserted.

Under voltage detection and performance throttling

Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is configured to receive temperature readings from the one or more thermal sensors. The control circuitry is configured to reduce a performance level of one or more controlled subsystems responsive to the comparison circuitry determining that at least one temperature reading from the one or more thermal sensors exceeds one of one or more threshold values. A software-based thermal control mechanism may also execute concurrently with the apparatus.

Thermal control apparatus and methodology

A method and apparatus for reducing a number of delay elements used in providing a delayed data strobe signal is disclosed. The method includes determining a number of delay elements of a master delay locked loop (DLL) needed to provide a calibrated delay of a clock signal (i.e. the data strobe). The method also include determining an integer number of half clock periods within the calibrated delay, and determining a second number of delay elements within the calibrated delay. If the integer number of half clock periods within the calibrated delay is zero, a slave DLL may be programmed with the first number of delay elements. However, if the number of half clock periods is non-zero, then a third number of delay elements is calculated by subtracting the second number of delay elements from the first number. Thereafter, the slave DLL is programmed with the third number of delay elements.

Memory controller half-clock delay adjustment

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San Francisco, CA, United States of America

Kiran Kattel