International Business Machines Corporation

Globalfoundries Inc.

Globalfoundries U.S. Inc.

Kiran K Narayan

Michael Richard Ouellette

Aravindan J Busi

Michael Anthony Ziegerhofer

Krishnendu Mondal

John Robert Goss

Paul J Grzymkowski

Kevin William Gorman

Deepak I Hanagandi

George M Belansek

A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Arbitration for memory diagnostics

Approaches for a memory built-in self-test (MBIST) are provided. The MBIST circuit includes a fail status register which receives a new fail signal value in response to a detection of a unique fail in a pattern, and a pattern mask register which stores at an end of the pattern a different value of the new fail signal value representative of the unique fail.

Memory built-in self-test (MBIST) test time reduction

Built-in-self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register

A system and method control an operation of a built-in self-test (BIST) of memory devices of an integrated circuit. The method includes generating count values using a program counter, and providing a first burst of instructions to the memory devices. The method also includes controlling a chip enable signal associated with each of the memory devices according to the count values during a wait period following the providing the first burst of instructions until a second burst of instructions is provided to the memory devices. The chip enable signal of each of the memory devices defines clock cycles at which the memory device is operated and clock cycles at which the memory device is idle.

Programmable counter to control memory built in self-test

Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.

Fast auto shift of failing memory diagnostics data using pattern detection

In a method of executing a BIST operation on IC memory arrays having a common BIST control unit, a first BIST sequence is initiated. Each address for the arrays is incremented. The BIST control unit receives a signal indicating a maximum valid address in the array is reached, receiving a plurality of maximum valid addresses, which are recorded. A single relatively highest maximum valid address is determined. A first mode, which prevents BIST testing, is engaged in each array having reached the maximum valid address. A second BIST sequence is initiated based on having received the signal indicating a maximum valid address is reached from all the arrays connected to the common BIST control unit. An address count is decremented from the single relatively highest maximum valid address. The first mode is disengaged for each array as the address count reaches each of the maximum valid addresses during the decrementing.

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Hyderabad Telangana, India

Kiran K Narayan