Microsemi Solutions (us), Inc.

Kiran Hanchinal

Kuan Hua Tan

Richard David Sodke

Gregory Arthur Tabor

Mansi Mehrotra

An apparatus and method for port mirroring in a plurality of Peripheral Component Interconnect express (PCIe) interfaces includes, for each PCIe interface, output transmission ports for transmitting data to a central processing unit (CPU), receiving input ports for receiving data from the CPU, port-mirror-in (PM_IN) ports, and port-mirror-out (PM_OUT) ports provided in a PHY layer instance. The PM_OUT ports of each PHY layer instance is coupled to the PM_IN ports of a next PHY layer instance such that the PHY layer instances of the plurality of PCIe interfaces are connected in a ring bus architecture for mirroring one or more ports of the output transmission ports or the receiving input ports of a first active PHY layer instance can be mirrored to output transmission ports of a second PHY layer instance.

Port mirroring for peripheral component interconnect express devices

A PCIe bus adapted for cross clock compensation of asynchronous clocks includes one or more PHY data ports provided in a PHY layer having a transmit clock (TCLK) for timing data transmitted to a peripheral device and a receive clock (RCLK) for timing data received from the peripheral device, one or more media access control (MAC) ports provided in a MAC layer having an interface clock (PCLK) for timing data transmitted to the PHY layer and data received from the PHY layer, wherein the PCLK and one or both of the TCLK and the RCLK are asynchronous, and one or more backpressure ports at an interface between the PHY layer and the MAC layer for controlling reading and writing of one of the PHY layer and the MAC layer. In some aspects, the PCLK frequency is set to be always greater than a maximum frequency of the RCLK and the TCLK.

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Bengaluru, India

Kiran Hanchinal