Intel Corporation

Kiran Ganesh

Naresh K Sehgal

Artour Levin

Miles F McCoo

A 2-dimensional placement system and method minimize reliability concerns arising from electromigration and self-heat while at the same time achieving a high layout density. The 2-dimensional placement method also uses a placement space with rows that have non-uniform sizes and are overlapping. According to one embodiment of the present invention, a computerized method of creating a layout for a circuit design includes receiving a circuit design and receiving at least one layout rule based on a reliability verification constraint for the circuit design. The computerized method further includes generating a layout for the circuit design through computer automated operations wherein the layout generated satisfies the at least one layout rule based on the reliability verification constraint received for the circuit design.

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Mountain View, CA, United States of America

Kiran Ganesh