Xilinx, Inc.

Kiran B Buch

Edwin S Law

Glenn A Baxter

Raymond C Pang

Mehul R Vashi

Jakong J Chu

A method and system for converting an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type. By identifying routing delays in a first architecture and what those same routing delays would be in a second architecture, the method and system verify that a design has been properly converted. The method and system are applicable to the conversion of programmable interconnect logic devices to mask programmable logic devices. For example, a method for verifying timing for a design implemented in a new device when the design is to be moved from an old device. The method is particularly useful for verifying timing in a mask programmable device (HardWire) when the design is being converted from a field programmable device (FPGA). By identifying routing delays of critical paths and paths for which a designer has established requirements, the method efficiently and reliably determines which paths in the new device need to be compared and verified. Reports generated according to the method of the invention greatly simplify the task of assuring a satisfactory conversion.

Method for verifying timing in a hard-wired IC device modeled from an FPGA

A hybrid HardWire device is provided that comprises a gate array core and a set of mask programmable I/O cells having I/O characteristics similar to those of an FPGA, i.e., sufficiently the same so the HardWire device can be used as a drop-in replacement for the FPGA with no redesign of the original system. Using this HardWire device, a user's design originally implemented in an FPGA can be emulated in the HardWire device, which then replaces the FPGA in the same board at a lower cost. In another embodiment, the I/O cells are mask programmable such that they can emulate the I/O characteristics of FPGAs from any of two or more FPGA families. This ability reduces the number of separate HardWire devices that must be designed, manufactured, tested, stored, and sold, and also simplifies the software required to convert designs to the new device. Some embodiments of the invention can also emulate other programmable devices such as PLDs.

Hardwire logic device emulating any of two or more FPGAs

A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. These interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

Programmable IC with gate array core and boundary scan capability

A method of implementing a boundary scan chain is provided using a programmable IC that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can 'swap the order' of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

Method of implementing a boundary scan chain

Hardwire logic device emulating an FPGA

A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. Theses interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.

Programmable I/O cell with dual boundary scan

A method is provided for scan testing that eliminates the need for balancing internal scan clock delays. According to the method of the invention, multiple scan clocks are provided, each being provided to a different set of flip-flops. The skew between the active edges of the scan clocks is deliberately increased to the point where each set of flip-flops has plenty of time to settle before the next set of flip-flops receives a clock pulse. Because scan testing is typically performed at clock speeds of only about 1 Megahertz, there is time for each of the scan clocks to pulse separately from all the others, without increasing the test time. The increased delay between scan clock pulses eliminates the need for balancing internal delays on the scan clock paths, thereby greatly reducing the number of placement and routing iterations required to achieve a functional design.

Test methodology based on multiple skewed scan clocks

A programmable IC is provided that includes dedicated boundary scan logic having a programmable boundary scan bit-order. Boundary scan cells are provided, each cell being capable of providing the boundary scan functions associated with one I/O pad. In a mask programmable device, dedicated tracks are provided for adding mask programmable interconnect lines. In other programmable ICs such as FPGAs or PLDs, programmable interconnect lines are provided. In either case, the interconnect lines are used to implement the boundary scan data chain. Using these lines, the programmed device can 'swap the order' of I/O cells in the boundary scan data chain, or leave cells out of the chain entirely. In one embodiment, the interconnect lines traverse each cell, programmably connecting the data inputs and outputs of adjacent or non-adjacent boundary scan cells. In other embodiments, the interconnect lines are physically located outside the boundary scan cells, either in a ring between the cell and the core or in the core itself.

Boundary scan chain with dedicated programmable routing

Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays, without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) is preserved by clustering together in the mask-configured integrated circuit (a gate array) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area. Test blocks are inserted in the gate array only where needed, i.e. at the output of any function generator that has connections external to the configurable logic block, and all flip flops are modified to also function as test blocks in a test mode. All logic blocks along asynchronous data paths in the FPGA are timing matched by delay elements in the mask-programmed substitute to preserve timing compatibility to the FPGA.

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Fremont, CA, United States of America

Kiran B Buch