Intel Corporation

Other

Kiran A Padwekar

Arvind Mandhani

Durgesh Srivastava

Sujoy Sen

Akhilesh Kumar

Phanindra Mannava

Suresh S Chittor

Ching-Tsun Chou

Rajee S Ram

Jesse Pan

Srinand Venkatesan

Sudhakar Bhat

Andalib Khan

Robert G Blankenship

Uday R Savagaonkar

Carlos V Rozas

Simon P Johnson

Abhishek Das

Keshavram N Murty

James A Stone

Embodiments of an invention for securing transmissions between processor packages are disclosed. In one embodiment, an apparatus includes an encryption unit to encrypt first content to be transmitted from the apparatus to a processor package directly through a point-to-point link.

Securing data transmission between processor packages

A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

Link level retry scheme

The ability to change from a first bus ratio to a second bus ratio without draining the transaction queues of a processor.

Method and system for fast frequency switch for a power throttle in an integrated device

A method and apparatus are provided for improving the performance of branch prediction using a combination of a speculative branch target buffer (SBTB) and an architectural branch target buffer (ABTB). According to one embodiment, speculative branch data is maintained for in-flight branches (i.e., those that have been fetched but not yet retired). A branch entry is speculatively allocated in a line of the SBTB after decoding an instruction containing a branch, such as a conditional branch, a return from a subroutine, a call to a subroutine, or an unconditional branch. Subsequently, the branch data associated with the branch entry is speculatively updated after branch prediction has been completed for the branch. Finally, the branch data is corrected after the branch has been executed. According to another embodiment, a novel branch prediction circuit includes both a speculative branch target buffer (SBTB) cache and an architectural branch target buffer (ABTB) cache. The SBTB cache contains multiple branch entries to maintain speculative branch data associated with in-flight branches. The speculative branch data includes a speculative history of taken/not-taken outcomes associated with the in-flight branches. The ABTB cache is coupled to the SBTB cache. The ABTB cache also includes multiple branch entries, however, they are for maintaining architectural branch data including the actual taken/not-taken outcomes associated with retired conditional branches.

Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)

Methods and systems for replaying arbitrary system executions are disclosed. A system includes a storage element, a memory hierarchy and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor executes instructions from the memory hierarchy. A replay handler is loaded into the memory hierarchy. The replay handler is executed for replaying at least one execution. In another embodiment, a method for replaying executions is disclosed. Normal execution of a processor is interrupted. A replay/restart kernel is loaded. At least one execution is replayed. Normal execution of the processor is resumed.

System and method for reproducing system executions using a replay handler

Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.

Systems and methods for testing processors

Code and instruction encoding extensions to a microcontroller architecture provide backward compatibility with an existing microcontroller while allowing significant performance enhancements as a result to the new architecture. An extension to provide additional instruction codes has been implemented while retaining backwards compatibility so that the instructions for the prior processor retain their functionality by utilizing one unused opcode in the prior processor's opcode map. In this connection, two modes of operation are provided, namely binary and source modes. The entire instruction set is available in both modes, but the encoding is different. In the binary mode, all of the instructions of the prior processor keep their encoding. The additional instructions have an ASH prefix, ASH being the single unused opcode. In source mode, some of the instructions from the prior processor known as register instructions have the AS prefix, thereby freeing up 160 opcodes for more important instructions. Since the register-based instructions of the new processor provide better performance than the instructions that they replace, there is no need to use the old register based instructions. Therefore, adding a byte and a state to the old register instructions results in a negligible penalty. In source mode, the instructions for the new processor do not require the AS prefix. This shortens these instructions by 1 byte in length and speeds up the execution by 1 state.

Instruction encoding techniques for microcontroller architecture

A circuit and method for handling a hardware conflict experienced by a branch target buffer. The method for handling the hardware conflict includes three steps. First, a determination is made to detect whether there is a write allocation to a branch target buffer (BTB) cache. If so, precedence is given to the write allocation by invalidating at least a first instruction pointer within a BTB pipeline. The first instruction pointer would have been used to read information from the BTB cache for branch prediction, absent the write allocation. Thereafter, the first instruction pointer is recovered by reloading it into the BTB pipeline in order to avoid missing its opportunity to predict. The two cycle delay caused by the invalidation and recovery of the first instruction pointer has little effect on the performance level of the circuit practicing this method of operation.

System for recovering from a concurrent branch target buffer read with a

A microprocessor or microcontroller architecture which utilizes a 64 byte-register file in a unique manner. The lowest 16 bytes of the register file can be accessed as 16 8-bit registers (R0-R15), the lowest 32 bytes can also be accessed as 16 32-bit (word) registers (WR0-WR30), and the entire register file can be accessed as 16 64-bit (double word or Dword) registers (DR0-DR60). In this manner, various combinations of 8/16/32-bit registers are provided without wasting the register file. While providing at least 16 8/16/32-bit registers, only four bits are necessary to encode a register, thereby allowing two byte register-to-register instructions. The register file and an instruction sequencer operate to provide the 64 byte-register file which can be accessed so that the lowest 16 bytes of the register file are accessed as 16 8-bit registers (R0-R15), the lowest 32 are accessed as 16 word registers (WR0-WR30), and the entire register file is accessed as 16 double word registers (DR0-DR60).

Register addressing for register-register architectures used for

A microcontroller or microprocessor architecture with a multiplexed address and data bus wherein the high order address bits are multiplexed with the low order data bits. Under this scheme, the low order address bits are connected directly to the memory and the high order address bits are latched by an address latch which captures the data on the bus when an address latch enable (ALE) signal is asserted. With the high order address bits multiplexed with the data bits, multiple data transfers can be performed without repeated address cycles since there is no need to place the high address bits which have already been latched on the multiplexed bus. The address and data buses are demultiplexed when the high order address bits are latched using ALE. When the address crosses the page boundary, the crossover is detected, by comparing the current high order address bits with the high order address bits of the previous bus cycle, and an address cycle is generated.

Growing community of inventors

Santa Clara, CA, United States of America

Kiran A Padwekar