Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Kinya Daio

Masaya Hirose

Tetsuya Oosaka

Kenji Watanabe

Takeshi Yamamoto

Masato Maede

Masahiro Gion

Hiroki Taniguchi

Tomoko Nobekawa

Hisaki Watanabe

Kazunari Ikeda

Takahisa Tokushige

In a semiconductor device including an N-line M-stage shift register circuit operated at high speed of, for example, several hundreds MHz. Input circuits input a common test pattern to each of pairs of shift registers in, for example, two lines out of the N lines. A plurality of outputs of the pairs of shift registers in the two lines are compared in comparators, and the comparison results are output. The N-line M-stage shift register circuit and the comparators are operated in synchronization with a clock signal at several hundreds MHz. Hence, even when the circuit scale (area) of the N-line M-stage shift register circuit is increased to involve apparent wiring delay, a defect in the shift register circuit can be detected at an actual speed.

Semiconductor device

A semiconductor deviceincludes a normal circuitand a voltage fluctuation detection circuitconnected to a power supplyin common with the normal circuit. The voltage fluctuation detection circuitincludes an inverting amplifier, a switching element, which is connected between input and output terminals of the inverting amplifier, and a capacitance elementconnected to the input terminal of the inverting amplifier. After the normal circuitand the switching elementare set to an operating state and ON state, respectively, when the switching elementis set to OFF state at an arbitrary time, charge corresponding to a power supply voltage Vcat that time accumulates in the capacitance element. After the normal circuitis set to a suspended state, a potential VDD of the power supplyis set to an arbitrary value, and the inverting amplifiercompares the value of a power supply voltage Vc with the voltage value Vccorresponding to the charge held in the capacitance element

The semiconductor device includes: an A/D conversion circuit for A/D-converting an analog input signal and outputting a resultant conversion result; and a computation circuit for performing, in synchronization with the A/D conversion circuit, computation for an updated conversion result without storing the updated conversion result every time the conversion result from the A/D conversion circuit is updated, to determine one computation result from a plurality of conversion results from the A/D conversion circuit and output the computation result.

A semiconductor device includes: an A/D converter; a digital processing circuit for performing processing based on conversion results from the A/D converter; a first test circuit for performing operation processing for checking a nonlinearity error (INLE) of the conversion results from the A/D converter; and a second test circuit for performing operation processing for checking a differential nonlinearity error (DNLE) of the conversion results from the A/D converter. The first test circuit performs only part of the operation processing for checking the nonlinearity error (INLE) of the conversion results from the A/D converter. The second test circuit performs only part of the operation processing for checking the differential nonlinearity error (DNLE) of the conversion results from the A/D converter. An operation processing section for performing the rest of the operation processing for checking the nonlinearity error (INLE) and the rest of the operation processing for checking the differential nonlinearity error (DNLE) is in a semiconductor test device.

Semiconductor device including A/D converter

The semiconductor device includes: an A/D conversion circuit; a digital processing circuit for performing processing based on conversion results of the A/D conversion circuit; and an output terminal for testing for outputting the conversion results of the A/D conversion circuit externally. The output of the conversion results from the output terminal for testing is made at timing that is different from timing of other conversion operation of which conversion results are to be outputted later and is longer in cycle than timing of conversion operation.

Semiconductor device having an A/D conversion circuit

There is provided a power switching circuit capable of completely breaking a current in an OFF state of a switch connecting power sources even when a voltage difference is generated between the power sources of a plurality of functional blocks separated from each other on an LSI chip. A gate control circuithas a control signal terminal INCNT, a first power imputer terminal IG, and a second power supply terminal IGas input terminals and has a first output terminal OGand a second output terminal OGas output terminals. The gate of a second P-type transistor Pis connected to the first output terminal OGof the gate control circuitand the gate of a second P-type transistor Pis connected to the second output terminal OGof the gate control circuit, wherein the first P-type transistor Pand the second P-type transistor Pare connected in series between a first power source VDDand a second power source VDDto form a switch section.

Growing community of inventors

Kyoto, Japan

Kinya Daio