Nec Corporation

Kabushiki Kaisha Toshiba

Nec Electronics Corporation

Kinji Kayanuma

Chosaku Noda

Yutaka Yamanaka

Hideaki Ohsawa

Toshiaki Iwanaga

Hiroharu Satoh

Hiromi Honma

Masaki Sano

Hiroharu Sato

The length of a format modulation area in an address segment is limited to be 25% of the address-segment length or less, and the position of the format modulation area is selectable two possible positions. Subsequently, where a CLV optical-disk medium is used, wobble modulation areas in adjacent recording tracks do not overlap each other in the radius direction.

Optical disk medium and optical disk apparatus

In a method of and an apparatus for creating a reproduced wobble signal by subtracting an estimated crosstalk signal, expressed by a sine waveform having a frequency approximately equal to the meandering frequency of grooves, from an original wobble signal and recording or reproducing an information pattern at a predetermined position of an optical disc, a carrier signal, which is caused to correspond to the meandering of the groove by being subjected to phase synchronization, is assumed based on the reproduced wobble signal, a crosstalk remaining component is estimated from the amplitude and phase of the region, which meanders in approximately the same phase as the estimated carrier signal in the reproduced wobble signal, and from the amplitude and phase of the region which meanders according to a signal different from the estimated carrier signal, and the estimated crosstalk is updated to cancel the remaining component.

Signal processing method of wobble signal, recording and reproducing method of optical disc, optical disc apparatus, program, and recording medium

A PLL circuit includes a phase comparing section, a low pass filter, a digital VCO circuit, and a frequency divider. The phase comparing section compares an inputted clock signal and a frequency-divided clock signal in phase to detect a phase difference. The low pass filter averages the phase difference outputted from the phase comparing section to output the averaged result as a frequency control input. The digital VCO circuit operates in synchronism with a reference clock signal, and generates a sync clock signal based on the frequency control input while a phase of the sync clock signal is controlled in units of predetermined resolution values. The predetermined resolution value is a 1/K (K is a natural number more than 1) of a period of the reference clock signal. The frequency divider frequency-divides the synch clock signal to generate the frequency-divided clock signal.

VCO circuit, PLL circuit using VCO circuit, and data recording apparatus the PLL circuit

A data bit stream is segmented into 4-bit data words and successively shifted two bits at a time. For each 4-bit data word a corresponding 3-bit code word is detected in a conversion table. Two higher significant bits of each data word is converted to the detected code word and two lower significant bits of the data word is then converted as two higher significant bits of a subsequent data word to a corresponding code word, so that a channel bit stream formed by a series of such code words has no consecutive 1's. A digital sum value of the channel bit stream is determined and a search is made for a code word '010' which is consecutive with a code word '000'. The detected code word &#x201c;010&#x201d; is replaced with a substitute code word &#x201c;000&#x201d; if the replacement results in the digital sum value approaching zero.

Data modulation method and apparatus

A recording data string is composed of a plurality of synchronous frames each of which has synchronous data and coding data. Data items in the coding data contributed to creation of the same column of the error correction code are arranged at regular intervals of E in the recording data string. A data segment length L is obtained by adding an additional synchronous frame to the recording data string. Wherein, a physical segment length A satisfies the equation L=mA, m is a natural number. And A is set indivisible by E.

Optical disk medium and optical disk recording and reproducing apparatus

A VCO, which good temperature characteristics, high frequency accuracy, and high phase accuracy is provided as an LSI, without making its master clock frequency operate the VCO high. The VCO includes a digital VCO, a phase modulator, and a frequency band limiting element. The digital VCO outputs an oscillating frequency clock and a phase difference lower than an output cycle resolution at the same timing as the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from positions near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference.

VCO with phase modulated output

In a code modulating method and a code modulating apparatus, a run length has an encoding rate of &#x2154; which is equal to that of (1, 7) modulation, and indicates the number of '0' bits between adjacent ones of '1' bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern &#x201c;1010101010101&#x201d; in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the &#x201c;0&#x201d; bit or &#x201c;1&#x201d; bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal. A frequency component of the signal is reduced from a maximum value of the frequency component by 20 dB or less as a power density at a frequency of {fraction (1/10,000)} or less of a channel clock frequency.

Code modulating method and code modulating apparatus, demodulating method and demodulating apparatus, and information recording medium

A method of replacement processing for secondary defects is provided that can maintain both the transfer rate and quality of write/read data at high levels. According to the method, a change-permitted range in which changes in the assignment of logical addresses is allowed is acquired, and when sectors having secondary defects due to write abnormalities are detected, replacement of sectors is carried out as long as changes in the assignment of logical addresses do not go beyond sectors in the change-permitted range by: omitting the secondary defect sectors by additionally registering the defective sectors in a slip replacement list, and shifting back the assignment of logical addresses as long as there are free sectors following the abnormal sectors.

Defective area replacement method and information writing/reading device

An equalizer is controlled to equalize a signal read from an optical disc. The equalized signal is supplied to a maximum-likelihood sequence detection circuit, in which a signal sequence is detected to be most coincident to the equalized signal among signal sequences meeting a state transition regularity. The equalizer operates for equalization, only when an error signal is detected in the vicinity of the end of a region having a code transition interval of more than number of minimum transition interval.

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Tokyo, Japan

Kinji Kayanuma