Seagate Technology Incorporated

Kinhing Paul Tsang

Bernardo Rub

Cenk Argon

Chandra Chuda Varanasi

Michael John Link

Alexander Kuznetsov

Kenneth R Burns

Bruce E Johnson

Robert E Kost

Krishna Rameshwara Malakapalli

A system includes an error correction encoder that encodes data and produces parity bits, and a parity bit processor that disperses the parity bits across the data, placing respective i-bit parity sub-blocks between selected multiple-bit data sub-blocks. The system also modifies one or more of the bits in predetermined positions in respective data sub-blocks based on the bits of the parity sub-blocks that precede them, such that the precoding does not sign invert the data sub-blocks.

System for providing running digital sum control in a precoded bit stream

A system includes an encoder that manipulates postcoded data and produces parity bits, and a parity bit encoder that produces encoded parity bits by inserting into the parity bits one or more flags with polarities, or states, that are selected to produce, after precoding, precoded parity bits that meet predetermined modulation constraints.

System for precoding parity bits to meet predetermined modulation constraints

A system includes a precoder-aware running digital sum (RDS) encoder that encodes user data as w-bit sub-blocks, to produce an encoded data block that meets block RDS constraints and consists of encoded data sub-blocks that meet sub-block RDS constraints. The sub-block constraints include the data sub-blocks having the same magnitude RDS before and after precoding. The encoder data block is further encoded using an error correction code to produce parity bits, and the parity bits are dispersed, as i-bit parity sub-blocks, between selected data sub-blocks to form a code word. The code word is then precoded to produce a precoded bit sequence for transmission over a channel. Sub-block run length limit ('RLL') constraints may also be included, such that the encoded data block meets both RLL and RDS, with the encoded data sub-blocks meeting respective RLL and RDS sub-block constraints.

Providing running digital sum control in a precoded bit stream using precoder aware encoding

In accordance with one or more embodiments data may be encoded into a code word that meets run length constraints and has a reduced running digital sum by encoding (N&#x2212;y)&#x2212;1 data bits and y flag bits into m first n-bit patterns that form a first N-bit code word, producing a second N-bit code word by encoding the (N&#x2212;y)&#x2212;1 data bits and the y flag bits into m second n-bit patterns in which corresponding first and second n-bit patterns combine to meet a first predetermined running digital sum threshold, and selecting the code word that satisfies selection criteria. The selection criteria may, for example, be the word with the fewest transitions, the word with the smallest running digital sum, and so forth.

Code design with decreased transition density and reduced running digital sum

A method and apparatus are provided for storing data. The method and apparatus generate a plurality of ECC codewords, which define a cooperative block. Each ECC codeword includes a plurality of information symbols and first and second sets of corresponding redundancy symbols. Shared redundancy symbols are generated for the cooperative block based on a combination of the second sets of redundancy symbols from the plurality of ECC codewords. A respective set of parity codewords is generated for the cooperative block based on the shared redundancy symbols. The second set of redundancy symbols for each ECC codeword in the cooperative block is derivable from the parity codewords. The cooperative block and the respective parity codewords are stored, without the second set of redundancy symbols, on a storage medium.

Shared redundancy in error correcting code

A method and apparatus are provided for decoding a sequence of code words into a sequence of data words. Each code word includes an encoded data word and an indicator bit. The encoded data word is extracted unchanged into a respective unencoded data word if an indicator bit has a first binary value and is extracted into the unencoded data word and then complemented if the indicator bit has a second, opposite binary value.

DC-free code having limited error propagation and limited complexity

A codeword for use in a communication channel is provided. A first segment of the codeword includes a plurality of bits having a running digital sum (RDS) and a second segment includes a plurality of bits based on the RDS of the first segment.

DC free code design with state dependent mapping

A method and apparatus are provided for encoding and decoding digital information. A sequence of data words is received, wherein each data word has a running digital sum (RDS). The sequence of data words is encoded into a sequence of corresponding code words, which has a current RDS. For each data word a binary symbol is added to the data word and the data word is selectively complemented as a function of the RDS of the data word and the current RDS of the sequence of code words to form the corresponding code word.

A method and apparatus are provided for encoding successive data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint, wherein at least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.

High rate running digital sum-restricted code

An encoding system for encoding digital data for transmission through a communication channel is described, which includes a DCF encoder and a parity encoder operatively coupled to the DCF encoder. The DCF encoder is adapted to receive a first data sequence, and to generate a first DCF code word and a new running digital sum as functions of the first data sequence and a pre-existing running digital sum, wherein the new running digital sum is limited to a maximum absolute value. The parity encoder is operatively coupled to the DCF encoder, and adapted to receive the first DCF code word from the DCF encoder, and to generate a first interleaved parity code word as a function of the first DCF code word, and to provide the first interleaved parity code word to a channel.

Generation of interleaved parity code words having limited running digital sum values

A method and apparatus are provided for encoding digital information. A sequence of successive data words are encoded into a sequence of successive code words according to a code, such that a running digital sum (RDS) of the sequence of successive code words is bounded and is constrained to predetermined, non-adjacent values at boundaries between the code words.

DC-free code design with increased distance between code words

A method of encoding digital information in a system is provided. The method includes receiving a sequence of user-bits and calculating a running digital sum (RDS) of the system. Also, a code word is generated based on the sequence of user bits and the RDS of the system to maintain the RDS of the system calculated with the code word to within a selected range. In one embodiment, the sequence of user bits is 19 bits and the code word is 20 bits.

Methods of encoding and decoding, as well as an encoding system and a digital communications system are provided for encoding data words into code words and decoding code words into data words. The data words are encoded according to a run-length-limited (RLL) code of 'k' constraint, the encoding producing u-bit non-zero code words. The 'k' constraint can be increased to a higher value by extending the u-bit non-zero code words to generate q-bit non-zero code words.

High rate run length limited code

Methods of encoding and decoding as well as an encoder and decoder are provided for encoding data words into codewords and decoding codewords into data words. The data words are encoded by mapping each data word into a number of data segments. Each data segment is then encoded to form a codeword segment that has the same number of bits as the data word segment. The codeword segments are concatenated to form the codeword. The codewords are decoded by decoding individual codeword segments into data word segments that are the same size as the codeword segments. The data word segments are then mapped into the data word, which has fewer bits than the total number of bits across all data word segments.

Method and apparatus for efficient encoding of large data words at high code rates

Data integrity is increased on mass-storage devices through a scheme whereby, a frame-based cyclic redundancy code (CRC) for each sector is recorded. A frame-based CRC is generated from the CRCs of the frames that compose a sector of data. In recording data, a CRC is generated from each frame, later, a master CRC is generated from the frame CRCs, then sector and master CRC are recorded on the mass-storage device medium. In retrieving data, the sector composed of frames and a master CRC are read, a plurality of CRCs are generated from each of the frames, a second master CRC is generated from the frame CRCs, and the master CRCs are compared to determine data integrity. In another embodiment, an input/output error detection and correction checksum (IOEDC), an error correction code (ECC) and a CRC are generated from a sector of data, and the IOEDC, ECC and CRC are stored on disc with the data sector.

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Plymouth, MN, United States of America

Kinhing Paul Tsang