Intel Corporation

Kingsum Chow

Khun Ban

Keqiang Wu

Peng-Fei Chuang

Shih-Lien L Lu

Christopher B Wilkerson

Haitham H Akkary

Zeshan A Chishti

Seth H Pugsley

John Du

Ying Feng

Robert L Scott

Aamer Jaleel

Jiang Ling Du

Brian C Tjaden

Yicong Huang

Sandeep R Nair

Thomas J Holman

Yong-fong Lee

Shirish Aundhe

Zhidong Yu

Sumeet Dua

Colin Cunningham

Sandhya Viswanathan

Yong J Chang

Ken T Deeter

Shruthi A Deshpande

A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described herein, includes tracking one or more factors relating to a plurality of data sets, evaluating the plurality of data sets based on the one or more factors. The evaluating may include speculating at least one of relevancy and accessibility of each of the plurality of data sets. The method may further include generating data scores, the data scores being associated with the plurality of data sets based on the evaluation of the plurality of data sets, performing a first comparison of the data scores of the plurality of data sets with a criteria score, and classifying each data set based on the first comparison. The classifying may include setting caching order for each data set of the plurality of data sets.

Mechanism for facilitating dynamic and proactive data management for computing devices

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Dynamic tuning of multiprocessor/multicore computing systems

Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

Techniques for controlling use of locks

A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.

Instruction and logic for run-time evaluation of multiple prefetchers

A computing device executes an application having a number of phases. The computing device collects performance data indicative of a number of performance attributes of the computing device during execution of the application. The performance attributes include page swap data, page fault data, and process queue data. The computing device merges data collected from a processor performance monitoring unit with data collected from an operating system of the computing device. The computing device partitions the performance data into a number of cluster models, applies a classification algorithm to each cluster model, and selects the cluster model with the lowest misclassification rate. The computing device associates each cluster of the cluster model to a phase of the software application. Compatible phases of software applications are scheduled based on the selected cluster model.

Identification of software phases using machine learning

Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution. The system may further include performance analysis circuitry configured to calculate a ratio of the first network traffic statistic to the second network traffic statistic and to estimate the application execution performance variation from the first sampling time interval to the second sampling time interval, wherein the estimation is proportional to the calculated ratio.

Estimation of application performance variation without a priori knowledge of the application

An online shopping basket is acquired by a buyer from an online store and is customized according to rules specified by the buyer. The buyer places zero or more items in the online shopping basket(s) before they are given to at least one shopper by the online store. The shopper(s) may further customize the online shopping basket(s) with rules that do not conflict with those specified by the buyer. The shopper(s) then place zero or more items in the online shopping basket(s) and return the basket(s) to the online store. Multiple online shopping baskets are merged into a single basket, and the buyer reviews the items in the merged online shopping basket and adds or removes items as necessary. The buyer then purchases the remaining items from the online store.

Rule-based transferable shopping basket for online purchases

In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Constraining prefetch requests to a processor socket

Methods and apparatus to provide cache management in managed runtime environments are described. In one embodiment, a controller comprises logic to determine an update frequency for an object in the runtime environment and assigning the object to an unshared cache line when the update frequency exceeds an update frequency threshold. Other embodiments are also described.

Cache management in managed runtime environments

Business process and apparatus for online purchases using a rule-based transferable shopping basket

Growing community of inventors

Portland, OR, United States of America

Kingsum Chow