Hewlett-packard Development Company, L.P.

King Wayne Luk

John Alan Wickeraad

Mark Gravel

Craig VanZante

A method includes generating an N-bit generated hash key for an M-bit search key. A data value associated with a matching hash key stored in a content addressable memory is retrieved. The matching hash key is then validated. The content addressable memory supports 2entries, wherein M&#x3e;N&#x3e;k.

Hash lookup table method and apparatus

A method stores data and check bits for that data within a memory chip. The memory chip stores the data and check bits in a plurality of pages contained in the memory chip, each page including a plurality of storage locations with each storage location having an associated address. The method includes receiving data to be stored in the memory, calculating check bits for the received data, mapping the data to addresses associated with the storage locations in a given page in the memory chip, mapping the check bits to addresses associated with the storage locations contained in the same page as the data, and storing the data and check bits in the page. The method may be applied to a single memory chip or to multiple memory chips.

Error checking and correction (ECC) system and method

One embodiment disclosed relates to an integrated circuit including on-chip logic analyzer circuitry. The on-chip logic analyzer circuitry includes a triggering circuit configured to receive a source data signal and start/stop timing signals. The on-chip logic analyzer circuitry further includes a compression circuit configured to receive an uncompressed data signal from the triggering circuit and to perform compression so as to form a compressed data signal. Other embodiments, aspects and features are also disclosed.

On-chip logic analyzer using compression

Timing of a write and read strobes for a memory having a double data rate (DDR) interface are automatically adjusted using write-read operations. A first and a second value of the write and read strobes are determined for a first write-read operation having the read data match the write data. A second write-read operation is performed for each of a plurality of third values for the write strobe at the second value for the read strobe set. A center of the third values having the read data match the write data is determined. A third write-read operation is performed for each of a plurality of fifth values for the read strobe at the fourth value of the write strobe. A center of the fifth values having the read data match the write data is determined. The timing of the write and read strobes are set to the centers.

Method for automatic adjustment of timing of double data rate interface

Systems, devices, and methods, including logic and/or executable instructions are described in connection with a buffer circuit. One buffer circuit includes a flip-flop based first-in first-out (FIFO) buffer having an input and an output, selection logic coupled in series with the FIFO buffer input, and a random access memory (RAM) FIFO coupled in parallel with the selection logic. The selection logic diverts incoming data to the RAM FIFO after the FIFO buffer is filled to a first capacity level, and reloads the FIFO buffer using data from the RAM FIFO until the RAM FIFO is emptied to a second capacity level. Data is extracted without read data latency from the output of the FIFO buffer as an output of the buffer circuit.

Buffer circuit

A method of caching counter values in network packet traffic sampling, includes: generating a pre-sample strobe; loading the pre-sample strobe into a counter cache; waiting for the next strobe; and generating a sample pulse when the next strobe arrives. An apparatus for counting packet values and for sampling the values, includes: a packet sampling processor including a counter cache, the packet sampling processor responsive to a pre-sample strobe so that the pre-sample strobe updates the counter cache, where a sample pulse is generated when the next strobe arrives.

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Elk Grove, CA, United States of America

King Wayne Luk