Intel Corporation

King Seng Hu

Vui Yong Liew

Bruce Moore

Thomas Ohe

A system and apparatus combining a hub and a function as a single chip compound device. A single serial interface engine (SIE) is shared between a hub endpoint and a function endpoint. The hub endpoint and function endpoint being integrated on a single chip. A single backend interface is coupled between the SIE and the endpoints. The backend interface selects which of the hub endpoints or the function endpoints can access the shared SIE at any time period. In one embodiment, a first address is associated with the hub and a second address is associated with the function. The backend interface selects between the hub and function by comparing a translated address received from the SIE with each of the first address and the second address. The result of the comparisons via suitable combinational logic serves as a select signal for a multiplexer between the hub/function and the SIE.

Compound device implementing hub and function endpoints on a single chip

An interrupt handler unit (IHU) for polling and arbitrating among interrupt sources and for generating a request for interrupt to a processor if winning priority is higher than an in-progress priority. The interrupt handler unit, upon acknowledgment by the processor, generates a vector address on an interface bus and at the same time pushes an acknowledged priority onto an in-progress priority (IPP) stack. The interrupt acknowledge is then provided to the appropriate interrupt source for the source to clear a pending flag. Upon a return from interrupt (RETI) instruction, the in-progress priority (IPP) stack is popped by the interrupt handler unit. The interrupt channels are time multiplexed based on interrupt state signals, and the individual interrupt sources can be masked. Interrupt related registers, (such as enable, priority, and flag) reside in the interrupt handler unit. The priority of an individual interrupt source is programmable using an interrupt priority registers, which are also provided in the IHU.

Method and apparatus for providing an interrupt handler employing a

A clock and reset unit for providing power saving modes to a pipelined microprocessor and for guaranteeing that power saving instruction is the last to be executed before the clocks stop, upon wake-up the next instruction executed is the first instruction in the interrupt service routine (ISR) and that upon return from the ISR, the instruction immediately following the power saving instruction is executed. A register is provided in the clock and reset unit for initiating a power saving mode. A software programmer selects a particular power saving mode by setting a corresponding bit in this register (i.e., writing a predetermined value to this register). A processor stalling signal generator for generating a signal that indicates to the processor that the peripheral is not ready to process a processor request (thereby causing the processor to insert wait states until the peripheral is ready) is provided. The clock and reset unit is also provided a signal from an interrupt handler indicating that the processor will be executing the ISR upon leaving the power save instruction. In response to this signal, the clock and reset unit de-assert the wait state request and brought the processor out of the power saving instruction.

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Penang, Malaysia

King Seng Hu