General Electric Company

King Owyang

Hamza Yilmaz

Nicholas A Schmitz

Louis J Ragonese

Saverio F Bevacqua

Mike F Chang

Robert G Hodgins

George L Gauffreau

Leonard Stein, Deceased

During fabrication of an insulated gate device, a drain-forming dopant having a relatively low diffusion coefficient is implanted along a substrate surface which overlaps the boundary between a to-be-formed vertical drain region and a to-be-formed adjacent channel region. During subsequent high temperature processing the low diffusion coefficient drain-forming dopant remains concentrated near the top surface of the substrate while other well-forming dopants, including an adjacent channel-forming dopant, which have relatively higher diffusion coefficients, diffuse to deeper regions of the substrate. The slow-diffusing drain-forming dopant retards lateral widening of the channel by the faster-diffusing channel-forming dopant just below the substrate surface to at least the depth of the channel inversion layer formed under the channel surface during device turn on. Retardation of lateral channel growth just below the substrate surface results in an insulated gate device of reduced channel length and improved transconductance. In a preferred embodiment, the slow-diffusing drain-forming dopant is implanted on the substrate surface together with a fast-diffusing drain-forming dopant, and the latter is diffused to a pinch off depth below the substrate surface to counteract pinch off resistance between opposed segments of an adjacent shallow channel-forming well.

IGT and MOSFET devices having reduced channel width

A disclosed MOSFET cell has a source region formed at the top surface of a semiconductor substrate. The top surface source region is electrically coupled to a conductive region at a bottom portion of the substrate by means of a vertical conduit which projects through the substrate from the top surface to the conductive region. A current exchanger is provided extending over the top surface of the substrate and coupling a top surface portion of the vertical conduit to the source region. The current exchanger makes ohmic contact with the source region and with the conduit region and shorts the two regions together such that majority carrier current of the conduit region will be 'converted' into majority carrier current of the source region and electrical continuity between the source region and the conductive region of the substrate is established. Respective source regions of multiple MOSFET cells may be interconnected in accordance with this method through a longitudinally extending conductive layer which is typically formed near the bottom surface of semiconductor substrates.

Mosfet structure with substrate coupled source

A semiconductor device having particularly low resistance connection to a portion thereof carrying substantial current is described. First and second electrodes are provided on a major surface of the semiconductor, the first electrode providing lateral contact to a control region of the semiconductor device; the second electrode providing low impedance vertical contact to the high current carrying region. A conductive plate is supported between upstanding spaced apart portions of the second electrode and is thereby vertically spaced apart from the first electrode.

Semiconductor device with built-up low resistance contact

An integrated circuit incorporating high voltage semiconductor devices which are controlled by low voltage semiconductor devices is disclosed, including a method for making the same. The low voltage devices which are capable of realizing complex logic functions on the same chip are realized with only one simple extra step in the fabrication process as compared with the process used to fabricate discrete high voltage power transistors. The process addition to implant the low voltage device does not significantly degrade the original capability associated with discrete power transistors. Both laterally developed and vertically developed devices are described. The integrated circuit combines I.sup.2 L logic with power Darlington transistors. A large area ion implantation permits one to fabricate both low and high voltage devices on one substrate. The resulting integrated circuit permits a plurality of loads to be controlled by a simple or complex control function.

Method of making an integrated circuit incorporating low voltage and

Integrated circuit incorporating low voltage and high voltage

A power transistor having improved turn-off characteristics and enhanced reversed second breakdown capabilities is described wherein the emitter of the transistor includes first and second regions, the first region being disposed within the second region and having lower gain than the second region. Turn off is enhanced as essentially no current flows under the lower gain first region during turn off thereby facilitating the removal of excess charge carriers when the device is in the turn-off stage.

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Baldwinsville, NY, United States of America

King Owyang