Siliconix Incorporated

Vishay-siliconix

King Owyang

Mike F Chang

Fwu-Iuan Hshieh

Yueh-Se Ho

Mohammed Kasem

Frank Kuo

Sen Mao

Jun W Chen

Dorman C Pitzer

Sze-Hon Kwan

Jan Van Der Linde

Lixiong Luo

Wei-Bing Chu

Hamza Yilmaz

Y Mohammed Kasem

Jowei Dun

Yuming Bai

Sam Kuo

Richard Kent Williams

Mohamed N Darwish

Kyle Terrill

Deva N Pattanayak

Kuo-In Chen

Robert Xu

Qufei Chen

Reuven Katraro

Kam Hong Lui

Ronald Wong

Oscar Ou

Serge Jaunay

Peter Wang

Chang-Sheng Chen

Calvin Choi

Reinhard Zachai

Jian Li

Hans-Jurgen Fusser

Jan V Linde

Thomas Toombs

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Semiconductor device with trench-like feed-throughs

A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.

Complete power management system implemented in a single surface mount package

A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.

Semiconductor including cup-shaped leadframe packaging techniques

An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.

High current density power field effect transistor

Semiconductor die package including cup-shaped leadframe

A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Semiconductor package including die interposed between cup-shaped lead frame and lead frame having mesas and valleys

A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide. The drain-drift region can be doped more heavily than the conventional 'drift region' that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The relatively flat dopant profile in the channel region provides an increased punchthrough voltage and low threshold voltage.

Trench MIS device having implanted drain-drift region and thick bottom oxide

Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys

Trench MIS device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same

Semiconductor assembly with package using cup-shaped lead-frame

A DMOS field effect transistor having its gate electrode located in a trench includes a lightly doped epitaxial layer overlying the usual epitaxial layer. The trench penetrates only part way through the upper epitaxial layer which is more lightly doped than is the underlying lower epitaxial layer. The lightly doped upper epitaxial layer reduces the electric field at the bottom of the trench, thus protecting the gate oxide from breakdown during high voltage operation. Advantageously the upper portion of the lightly doped upper epitaxial layer has little adverse effect on the transistor's on resistance.

Field effect Trench transistor having lightly doped epitaxial region on

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Atherton, CA, United States of America

King Owyang