International Business Machines Corporation

University of California

Conexant Systems, Inc.

King-Ning Tu

Richard D Thompson

Cyprian Emeka Uzoh

Hariklia Deligianni

Scott Kevin Reynolds

Panayotis Constantinou Andricacos

Ya-Hong Xie

Chao-Kun Hu

James M Harper

Dale J Pearson

Chang-Ching Yeh

Kie Y Ahn

Thomas H DiStefano

Subramanian Srikanteswara Iyer

Bin Zhao

Leathen Shi

Robert Rosenberg

Christopher H Bajorek

Milan Paunovic

Yuhuan Xu

Moshe Eizenberg

William H Carlson

Jia-Sheng Huang

John E Baglin

Boryeu Tsaur

Peter A Psaras

Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications

An improved dielectric material having pores formed therein and a method for forming the material are disclosed. The material is formed of a polymer. Pores within the polymer are formed by forming solid organic particles within the polymer and eventually vaporizing the particles to form pores within the polymer.

Method of forming dielectric material suitable for microelectronic circuits

A method of making Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin is disclosed for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Method of making copper alloys for chip and package interconnections

Copper alloys containing between 0.01 and 10 weight percent of at least one alloying element selected from carbon, indium and tin for improved electromigration resistance, low resistivity and good corrosion resistance that can be used in chip and package interconnections and a method of making such interconnections and conductors by first forming the copper alloy and then annealing it to cause the diffusion of the alloying element toward the grain boundaries between the grains in the alloy are disclosed.

Copper alloys for chip and package interconnections

Dopant activation in heavily boron doped p.sup.+ --Si is achieved by applying electric current of high density. The p.sup.+ --Si was implanted by a 40 KeV BF.sup.2+ at an ion intensity 5.multidot.10.sup.15 ions per cm.sup.2 and annealed at 900.degree. C. for 30 minutes to obtain a partial boron activation according to conventional processing steps. To obtain additional activation and higher conductivity, current was gradually applied according to the invention to a current density of approximately 5.times.10.sup.6 A/cm.sup.2 was realized. The resistance of the p.sup.+ --Si gradually increases and then decreases with a precipitous drop at a threshold current. The resistance was reduced by factor of 5 to 18 times and was irreversible if an activation current threshold was reached or exceeded. The high-current-density-dopant activation occurs at room temperature.

Dopant activation of heavily-doped semiconductor by high current

In the design of stud and conducting line joints, the conducting line is extended beyond the stud without any significant overhang of the line in the width direction for minimizing induced stress in order to reduce voids and crack growth in the region where the connecting line is joined to the stud. The preferred length of the extension is in the range approximately between one-quarter and twice the stud dimension. The design is applicable, but not limited to, multilevel integrated circuits used in computers and other electrical devices.

Asymmetric studs and connecting lines to minimize stress

An epitaxial conductor and a method for forming buried conductor patterns is described incorporating a layer of single crystalline silicon, a pattern formed therein such as a trench, a layer of metal silicide epitaxial formed on the bottom surface of the pattern or trench, a layer of silicon epitaxially formed thereover, and a layer of metal silicide epitaxially formed over the silicon layer. The invention overcomes the problem of twinning defects in the top surface of epitaxial silicide layers.

Formation of 3-dimensional silicon silicide structures

An apparatus and method for forming an interconnect through an opening or on an insulation layer with the coefficient of thermal expansion of the interconnect adjusted to reduce the thermal stress between the interconnect and the insulation layer is described incorporating the steps of forming a solid solution of a binary alloy including germanium and aluminum or a ternary alloy including aluminum, germanium and a third element, for example silicon, and forming a precipitate from the solid solution at a reduced temperature with respect to the temperature of forming the solid solution whereby the volume of the precipitate including germanium and the remaining solid solution is larger than the volume of the original solid solution.

Aluminum-germanium alloys for VLSI metallization

An improved thin film barrier with three layers where an interlayer is between barrier layers on each side, the interlayer serving as an atom energy sink. The improved barrier in the diffusion of Cu through Ni into Au where the barrier layers are Ni and the interlayer is Au, making a stack of AuNiAuNiCu, reduces the Cu present in the external Au layer after prolonged annealing in the vicinity of 0.2% atomic.

Barrier improvement in thin films

An electrical contact between two film members that is stable over all conditions encountered in processing and over the device lifetime. The contact has a central multi-element diffusion barrier alloy layer having at least one elemental ingredient that does not react with either film member and at least one other elemental ingredient that reacts with the adjacent film member to form an intermediate layer between the diffusion barrier layer and each film member. A contact between aluminum wiring and silicon devices on an integrated circuit chip is provided with a diffusion barrier layer of for example, WPd with an intermediate layer on both sides, one side being PdSi next to the silicon and the other being AlPd.sub.3 next to the aluminum.

Electrical multilayer contact for microelectronic structure

A structure and method are described for forming different metal silicide phases, using the same metallurgy and the same processing steps. A layer of metal is deposited on a silicon substrate and is heated to thermally convert the metal-silicon combination to a metal silicide. The metal silicide phase which forms is strongly dependent upon the dopant and doping level in the silicon substrate, for various combinations of metal and dopant. Thus, different metal silicides can be formed on different regions of the substrate in accordance with the dopant and doping levels in those different regions, even though the process steps and metallurgy are the same. These different metal silicides can be tailored for different applications, including ohmic contacts, diode barrier contacts, interconnection lines, gate contacts, and diffusion barriers.

Dopant control of metal silicide formation

A 3D epitaxial structure is described in which metal compounds are formed in a semiconductor layer, the metal compounds being epitaxial with the semiconductor layer and having a top surface which is planar with the top surface of the semiconductor layer. Onto this another layer can be epitaxially grown, such as an additional semiconductor layer. The technique for forming such a structure utilizes a starting material for metal compound formation which leaves a residue that is preferentially etched in order to preserve the embedded metal compound and to leave a substantially planar surface comprising the metal compound epitaxial regions and the unreacted surface regions of the semiconductor layer.

Method for making planar 3D heterepitaxial semiconductor structures with

In the practice of this disclosure, rare earth disilicide low Schottky barriers (.ltorsim.0.4 eV) are used as low resistance contacts to n-Si. Further, high resistance contacts to p-Si (Schottky barrier of .gtorsim.0.7 eV) are also available by practice of this disclosure. A method is disclosed for forming contemporaneously high (.gtorsim.0.8 eV) and low (.ltorsim.0.4 eV) energy Schottky barriers on an n-doped silicon substrate. Illustratively, the high energy Schottky barrier is formed by reacting platinum or iridium with silicon; the low energy Schottky barrier is formed by reacting a rare earth with silicon to form a disilicide. Illustratively, a double layer of Pt/on W is an effective diffusion barrier on Gd and prevents the Gd from oxidation.

Rare earth silicide Schottky barriers

It has been discovered for the practice of this disclosure that a particular ion radiation treatment of amorphous SiO.sub.2 thin film, with a subsequent annealing procedure, improves the dielectric breakdown property of the film. The treated SiO.sub.2 film is found to be substantially more dense than a comparable untreated SiO.sub.2 film. It is theorized for the practice of this disclosure that the physical mechanism which produces the densification of the SiO.sub.2 film may be responsible for the enhanced dielectric properties of the film. Such an improved film is especially useful as the gate insulator layer in an insulated-gate electrode field-effect transistor device, and as an insulating layer for electrically separating two metallic films in a thin film integrated circuit. Such SiO.sub.2 thin films are useful in integrated circuit technology because the electrical insulation property thereof is considerably improved, e.g., in metal-oxide-semiconductor field effect devices in which the gate insulation is relatively thin, e.g. less than 500A, and in metallic magnetic-bubble devices in which a thin SiO.sub.2 layer is used to separate the sense element from the conductive magnetic film.

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Los Angeles, CA, United States of America

King-Ning Tu