United Microelectronics Corp.

Other

King-Lung Wu

Chuan-Fu Wang

Kun-Chi Lin

Tzung-Han Lee

Sun-Chieh Chien

Jason Jyh-shyang Jenq

Jung-Chao Chiou

Alex Hou

Cheng-Shuen Hu

A method of fabricating a node contact on a substrate, which contains a first conductive device and an insulating layer covering the substrate and the first conductive device, includes forming at least two conductive lines on the insulating layer, wherein the conductive lines are separated by a first distance; forming at least two second conductive devices on the insulating layer, wherein the second conductive devices are separated by a second distance, and wherein one of the conductive lines and one of the second conductive devices are separated by a third distance, and wherein both the first and second distances are greater than the third distance; forming an isolation layer of a thickness on the substrate to cover the insulating layer, the conductive lines and the second conductive devices, wherein the isolation layer comprises a dished area located between the second conductive devices; removing a portion of the isolation layer to form a spacer around the second conductive devices, and to deepen the dished area to form an opening exposing the insulating layer; deepening the opening to expose the first conductive device; and filling the opening with a conductive material.

Method of fabricating node contacts

The invention provides a method for fabricating bitlines, including the following steps: providing a semiconductor substrate having a contact opening, which opening exposed a diffusion region in the substrate or a polysilicon layer of a wordline; forming a polysilicon layer to cover the opening and contacting the exposed surface of the diffusion region or the polysilicon layer of the wordline; forming a tungsten silicide layer to cover the polysilicon layer; performing a ion implantation step with high energy and high dosage to damage a contact surface between the bitline and the wordline or a contact surface between the bitline and the diffusion region; forming a better contact surface between the bitline and the wordline or a better contact surface between the bitline and the diffusion region using thermal annealing in the subsequent steps, thereby reducing contact resistance between the bitline and the wordline or between the bitline and the diffusion region.

Method for fabricating bitlines

The present invention provides a method for landing pads in the semiconductor devices, comprising the following steps: providing a semiconductor substrates with a plurality of active regions, a plurality of gate structures above the active regions and a plurality of source/drain regions, while each gate structure comprises a top cap layer and sidewall spacers; forming a conductive layer over the substrate; removing a portion of the conductive layer above the gate structure using the top cap layer of the gate structure as a stop layer, so that a height of the conductive layer is lower than a height of the gate structure; forming a patterned mask layer, right above the active regions, over the substrate; performing an etching step to define the conductive layer above the active regions; and removing the patterned mask layer and forming landing pads on the active regions.

Method for forming landing pad

An isolation layer is formed on a substrate of a semiconductor wafer. At least one recess is formed in the isolation layer by way of a photo-etching-process. A two stage in-situ doped deposition process is then performed to form a first doped amorphous silicon (&agr;-Si) layer and a second doped amorphous silicon (&agr;-Si) layer doping concentration of the second doped amorphous silicon (&agr;-Si) layer being less than that of the first doped amorphous silicon layer. A dielectric layer is formed to fill the recess, and a planarization process removes portions of the second doped amorphous silicon layer, the first doped amorphous silicon layer and the dielectric layer on the surface of the isolation layer. Finally, the dielectric layer and the isolation layer are removed, and a hemi-spherical grain (HSG) process is performed to form a rough surface with a plurality of hemi-spherical grains on the surface of the second doped amorphous silicon layer.

Method of forming a lower storage node of a capacitor

The present invention provides a method of automatically defining a landing via on a semiconductor wafer. The present invention involves first forming a conductive layer and a photoresist layer on the surface of the semiconductor wafer. Then, patterns of a plurality of word lines are defined on the surface of the photoresist layer, and patterns of a plurality of auxiliaries are defined around the area predetermined to form the landing via between each two word lines on the surface of the photoresist layer. Thereafter, the patterned photoresist layer is used as a hard mask to etch the conductive layer to form each word line on the semiconductor wafer, and to simultaneously form the auxiliaries around the area predetermined to form the landing via. Finally, a plurality of spacers are formed around each word line and each auxiliary dovetail together to form a landing via hole and to automatically define the position of the landing via.

Method of automatically defining a landing via

A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.

Method of fabricating a bottom electrode

A method for forming an inner-cylindrical capacitor without top electrode mask is disclosed. The method includes a step of a trench formed on the substrate. The trench structure with a conductive layer as a first lower electrode. The first poly spacer as second lower electrode of inner-cylindrical capacitor formed on sidewall of the trench, and furthermore a dielectric layer is formed by depositing on sidewall of first poly spacer and a floor of the cylindrical trench. Then, the second poly spacer formed on sidewall of dielectric layer. The poly plug is formed by depositing polysilicon layer and polished by chemical mechanical polishing (CMP) process. Thus, an inner-cylindrical capacitor is generated.

Method for forming inner-cylindrical capacitor without top electrode mask

A method of manufacturing a dynamic random access memory cell. A substrate having a transistor therein is provided. A first dielectric layer is formed over the substrate and the transistor. A bit line having a cap layer thereon is formed over the first dielectric layer. A protective layer is formed over the substrate covering the bit line. A second dielectric layer is formed over the protective layer. The second dielectric layer is etched in a self-aligned process. The etching continues penetrating the protective layer and the first dielectric layer until the substrate is exposed so that a node contact opening and an opening for forming the lower electrode of a capacitor are formed at the same time. Thereafter, polysilicon material is deposited into the node contact opening and the lower electrode opening to form a polysilicon layer. The upper surface of the polysilicon layer is slightly below the lower electrode opening. A spacer is formed on the sidewalls of the lower electrode opening above the polysilicon layer. Using the spacers as a mask, the polysilicon layer is etched to form a lower electrode with a recess groove above the node contact opening. The second dielectric layer and the spacers are removed. To complete the fabrication of the DRAM cell capacitor, a dielectric layer is formed over the lower electrode and an upper electrode is formed over the dielectric layer.

Method of manufacturing dynamic random access memory cell

A method for forming a capacitor in DRAM is disclosed. The method includes: providing a conductor defined on a first dielectric layer; forming a second dielectric layer on the conductor; then forming a polysilicon layer on the second dielectric layer, the polysilicon layer serves as an etching mask; next, etching the second dielectric layer; removing said polysilicon layer; etching said conductor; and finally removing said second dielectric layer.

Method for forming a capacitor in dram

A method of fabricating a bottom electrode is described. A substrate having a first conductive layer therein is provided. A first dielectric layer is formed over the substrate. A plurality bit lines is formed over the first dielectric layer. A conformal liner layer is formed over the first dielectric layer to cover the plurality bit lines. A second dielectric layer is formed over the conformal liner layer. An opening is formed in the second dielectric layer. The opening exposes a portion of the conformal liner layer between the bit lines and the conformal liner layer on portions of the bit lines. A conductive spacer is formed on a sidewall of the opening to expose a portion of the conformal liner layer between the bit lines. The exposed portion of the conformal liner layer between the bit lines is removed. The first dielectric layer exposed by the conductive spacer and the second dielectric layer are removed to form a node contact opening in the first dielectric layer. The node contact opening exposes the conductive layer. A second conductive layer is formed to fill the node contact opening.

A method of fabricating a bottom electrode is described. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines are formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.

A fabrication method for a borderless buried bit line is described. A substrate wherein a plurality of word lines and source/drain regions formed thereon is provided. A first insulation material is formed over the substrate and a node landing pad is formed in the first insulation material, wherein the node landing pad is covered by a second insulation material. A bit line contact is further formed in the first insulation material, wherein the bit line contact is covered by a third insulation material. Therefore, a trench is further formed along the sides of the bit line contact, traversing across the first insulation material. A partial filling of the trench with a conductive material, followed by filling the trench with a fourth insulation layer to complete the formation of the buried bit line.

Fabrication method for a buried bit line

A method of fabricating a node contact hole is disclosed. The fabrication includes the steps as follows. At first, the first interpoly dielectric (IPD1) layer is formed over the semiconductor substrate. The landing pad is formed in the first interpoly dielectric layer. The polycide bit line is formed on the first interpoly dielectric layer. Afterwards, the second interpoly dielectric (IPD2) layer is formed over the first interpoly dielectric layer. Next, the defined photoresist layer is formed on the second interpoly dielectric layer, then using reflow and curing processes to form the heated photoresist layer. Afterwards, a portion of the second interpoly dielectric layer is firstly etched, using the heated photoresist layer as a mask. The depth is formed in the second interpoly dielectric layer. Then the heated photoresist layer is removed. Next, in order to the silicon nitride layer and the polysilicon layer are deposited over the second interpoly dielectric layer. Then, the polysilicon layer is etched back to expose the silicon nitride layer. Afterwards, a portion of the second interpoly dielectric layer is secondly etched to expose the land pad. Next, in order to the polysilicon layer and the silicon nitride layer are removed over the second interpoly dielectric layer. The node contact hole is formed in the second interpoly dielectric layer.

Method of fabricating node contact hole

A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer. The second polysilicon layer, the polysilicon spacer, a portion of the silicon-oxy-nitride layer, a portion of the tungsten silicide layer, and a portion of the first polysilicon layer is Sequentially etched to expose the interpoly dielectric layer, using the silicon oxide layer as a hard mask. Afterwards, the silicon oxide layer is removed on the silicon-oxy-nitride layer. Finally, the narrow bit line structure is formed over the landing pad.

Method of fabricating a narrow bit line structure

A method of forming a dual cylindrical capacitor on a semiconductor substrate having at least a device isolation structure and a transistor thereon is provided, wherein the transistor includes at least a gate and a source/drain region. A first insulation layer and a second insulation layer are formed on the substrate. An opening comprising an lower part penetrating through the first insulation layer and an upper part penetrating through the second insulation layer is formed to expose the source/drain region. A conductive layer is formed on the second insulation layer to fill the lower part of the opening and to cover a surface of the upper part of the opening. A spacer is formed on a part of the conductive layer on a side wall of the larger opening. A conductive spacer is formed on the spacer. The spacer is removed.

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Tainan Hsien, Taiwan

King-Lung Wu