Marvell International Limited

Other

King Chun Tsai

Lawrence Tse

George Chien

Xiaodong Jin

Sang Won Son

Wayne A Loeb

Yonghua Song

Patrick Clement

Shuran Wei

Tyson Leistiko

Sehat Sutardja

David Cousinard

Yuan-Ju Chao

Qiong Sun

Leycheoh Lim

Hui-Ling Lou

Songping Wu

Kedar Shirali

Yungping Hsu

Alireza Shirvani-Mahdavi

Swee-Ann Teo

Gang Liu

Hsiao-Cheng Tang

Donghong Cui

Weijun Yao

Hua Qian

Sang Wong Son

Alireza Shirvani Mahdavi

Dong Hun Shin

Apparatus, systems, and methods implementing techniques for calibrating a filter circuit. A comparator generates an output based on a filter output amplitude signal and a reference amplitude signal. A calibration logic unit receives the comparator output and produces a component code that is used by the filter circuit to adjust one or more component values.

Iterative filter circuit calibration

A system including a component of a transceiver, a comparator, a counter, and a calibration circuit. The component receives an input signal comprising packets and based on the input signal, generates output signals to transmit the packets. The comparator compares the output signals to generate a comparison signal. The counter counts cycles of a clock signal to provide a count value. The control device, based on the comparison signal, transitions the counter between incrementing the count value and decrementing the count value. The calibration circuit operates in first and second calibration modes; during the first calibration mode, calibrates the component until the counter transitions a predetermined number of times between incrementing the count value and decrementing the count value; and during the second calibration mode, calibrates the component until (i) the counter transitions between incrementing and decrementing the count value, or (ii) counts a predetermined number of cycles.

Apparatus and method for calibrating a component of a transceiver via a calibration circuit operating in different calibration modes

A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.

Receiver employing selectable A/D sample clock frequency

A method includes, in at least one aspect, connecting an input of a bias circuit and an output of the bias circuit to another circuit while the other circuit is in a first power mode, such that the bias circuit has an operating state corresponding to the first power mode; switching the input of the bias circuit and the output of the bias circuit from the other circuit to a dummy circuit when a power mode of the other circuit is changed from the first power mode to a second power mode; and maintaining the bias circuit at the operating state corresponding to the first power mode using the dummy circuit while the other circuit is in the second power mode.

Method and apparatus for reducing wake up time of a powered down device

A filter includes, in at least one aspect, one or more differential inputs to receive one or more differential input signals, a first filter stage to provide one or more primary poles corresponding to a first frequency associated with the one or more differential input signals, a second filter stage coupled with the first filter stage to provide one or more secondary poles corresponding to a second frequency associated with the one or more differential input signals, the second frequency and the first frequency having a predefined relationship, and one or more differential outputs coupled with the second filter stage to provide one or more differential output signals.

Spurious component reduction

A transceiver including a transceiver component with a first and second inputs and an output. The transceiver is configured to (i) receive an input signal having packets via the first input and (ii) generate output signals at the output based on the input signal. The transceiver further includes a first comparator configured to compare the output signals and generate a first comparison signal; a register configured to store the first comparison signal; a calibration circuit is configured to generate a current signal based on the first comparison signal to adjust a current in the transceiver component; and a signal generator is configured to generate a reference signal based on the current signal. The transceiver component is configured to (i) based on the current signal, adjust a performance parameter of the transceiver at times synchronized with the packets and (ii) generate the output signals based on the current signal and the reference signal.

Frame/packet-based calibration for wireless transceivers

A dummy circuit is provided to which a bias circuit of an low noise amplifier (LNA) can be coupled to during power down of the LNA. The dummy circuit maintains the bias circuit at an approximately normal operating state to reduce wake up time of the LNA.

A radio frequency (RF) receiver includes a local oscillator (LO) module that receives a control signal and that generates a LO signal at a LO frequency that is based on the control signal, a LO mixer module that generates an intermediate frequency (IF) signal based on a radio frequency (RF) signal and the LO signals, a complex intermediate frequency (IF) mixer module that generates a baseband signal based on the IF signal and an IF oscillator signal, and a channel monitoring module that generates the control signal based on the baseband signal.

Adaptive FM/AM radio architecture

In a method and system for controlling gain in an RF receiver, an RF signal is analyzed over different attack and decay windows, from which the receiver determines (1) if the signal is in an attack condition with dip values below a threshold level thus indicating a need for increasing signal gain, or (2) if the signal is in a decay condition with threshold values above a threshold level thus indicating a need for decreasing signal gain. The receiver applies attack and decay windows of different sizes and in an asynchronous manner to create a gain control scheme that is insensitive to transient effects such as channel interference and deep fading that affect the intensities of an in-band signal.

RF-AGC scheme insensitive to channel interference and deep fading

An adjustable, segmented amplifier including (i) a first fixed stage configured to amplify an analog signal in accordance with a fixed amplification, and provide the analog signal amplified in accordance with the fixed amplification to a first common node. The adjustable, segmented amplifier further includes an adjustable stage comprising a plurality of independently selectable parallel amplifier segments, wherein the adjustable stage is configured to (i) amplify the analog signal provided to the first common node in accordance with an adjustable amplification that is adjustable depending upon a number of the independently selectable parallel amplifier segments having been selected to amplify the analog signal provided to the first common node, and (ii) provide the analog signal amplified in accordance with the fixed amplification and amplified in accordance with the adjustable amplification to the second common node.

Adjustable segmented power amplifier

A low noise amplifier includes an input stage. The input stage includes a first device configured to receive an input signal. A second device is connected to the first device. The second device has a predetermined input impedance. The input stage is configured so that a change in the input signal to the first device causes a linearly proportional change in a conductance of the first device. A voltage at a junction between the first device and the second device remains substantially constant due to the predetermined input impedance of the second device.

Method and apparatus for an LNA with high linearity and improved gain control

An electrostatic discharge (ESD) circuit operable to protect an internal circuit from ESD events and protect the internal circuit from high-side supply noise.

Method and apparatus for improving supply noise rejection

A receiver includes a Gilbert cell mixer comprising an input transconductance stage. The input transconductance stage includes first and second transistors receiving an input signal and providing a first gain characteristic that is substantially non-linear over an operating frequency range of the receiver. Third and fourth transistors receive the input signal and provide a second gain characteristic that is substantially non-linear over the operating range of the receiver. A combined gain characteristic of the input transconductance stage is based on the first and second gain characteristics and is substantially linear over the operating frequency range of the receiver.

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San Jose, CA, United States of America

King Chun Tsai