Vitelic Corporation

King C Wang

James T Koo

In-Nan Wu

Craig S Thrower

Jon C Zierk

Francis C Hung

A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.

CMOS logic circuit with output coupled to multiple feedback paths and

The present invention is a controller for producing a dual port function from a single port memory with an improved memory cycle time. An address or control signal transition for one port generates an access request signal for that port. The access request signal both (1) blocks an access request by the other port for its duration and (2) generates a series of signals for a memory access for the selected port. A multiplexer for providing addresses to the memory core from two ports is switched to select a second port while a first port access is in progress. The output of the multiplexer is not enabled until the memory core access is completed. Thus, the set-up time for the second set of addresses is allowed to overlap the memory core access time for the first set of addresses thereby reducing overall cycle time.

Growing community of inventors

El Monte, CA, United States of America

King C Wang