Semiconductor Components Industries, LLC

Fairchild Korea Semiconductor Ltd.

Kinam Song

Jinkyu Choi

Wonhi Oh

JunHo Lee

Samuell Shin

Seunghyun Hong

Hyunsoo Bae

BumSeung Jin

Tai-Hua Chen

Yi-Feng Hsia

Tae-sung Kwon

Taesung Kwon

Sangmin Park

Seungjae Lee

A circuit and method for detecting a failure of a switching power device is disclosed. The circuit and method utilize a Kelvin connection of a four-terminal configuration of the switching power device to sense a resistance of at least one wire-bond. The resistance corresponds to a defect or defects in the at least one wire-bond and so it can be used to detect a failure before damage occurs. A threshold used for detecting the failure can be adjusted to accommodate variations in the switching power device and/or the application in which it is being used. Additionally, the failure detection is carried out at a period after the switching power device is turned ON to prevent switching transients from affecting the detection.

Circuit and method to detect defects in a power switching device

An electronic circuit includes a gate driver circuit. The gate driver circuit receives an input signal and a signal corresponding to a current through a switch, and produces, using the input signal, an output signal for controlling the switch. In response to the input signal being de-asserted, the gate driver circuit may turn the switch off at a normal turn-off rate when the current through the switch is less than an overcurrent (OC) threshold, and at an OC turn-off rate that is slower than the normal turn-off rate when the current through the switch is greater than the OC threshold.

Gate driver circuit

A circuit for controlling a gate driver includes a delay circuit, a first logic circuit, and a second logic circuit. The delay circuit receives a first turn-off signal and produces a second turn-off signal by delaying an assertion of the first turn-off signal by a freewheeling duration. The first logic circuit receives the first and second turn-off signals and produces a smart turn-off signal by asserting the smart turn-off signal when the first turn-off signal is asserted and the second turn-off signal is not asserted. The second logic circuit receives a restart signal and the smart turn-off signal and produces a smart reset signal by asserting the smart reset signal when the restart signal and the smart turn-off signal are de-asserted, and de-asserting the smart reset signal when one or more of the restart signal and the smart turn-off signal are asserted.

Smart turn-off for gate driver circuit

A circuit for controlling a power converter includes a pulse generator generating a first pulse signal and a second pulse signal in response to an input signal, the first pulse signal being asserted at a given time interval or thereafter after the input signal has been de-asserted, a level-shift circuit shifting a level of the first pulse signal to generate a first shifted signal and to shift a level of the second pulse signal to generate a second shifted signal, a logic circuit controlling a first-side switching device in response to the first and second shifted signals, and an output node outputting an output signal. The first-side switching device is coupled to a second side-switching device at the output node.

Control of pulse generator in driving control device

An UVLO circuit according to an aspect of the present invention includes: a power-on reset (POR) circuit generating an output based on a first current that flows according to an increase of a power supply voltage and not operating in a normal state of the power supply voltage; and a logic operation unit generating a reset signal according to an output of the POR circuit and an output based on a result of comparison between a sense voltage that corresponds to the power supply voltage and a predetermined reference voltage.

Power-on reset circuit and under-voltage lockout circuit comprising the same

A pulse generator includes a first inverter configured to inverse an input pulse and output a result, a second inverter configured to inverse the output of the first inverter and output a result, a clamp inverter configured to generate a clamping voltage by clamping the output of the second inverter and generate an output pulse through a source follower which operates according to the clamping voltage, and a temperature compensator configured to compensate for variations in the clamping voltage caused by temperature change.

Pulse generator and driving circuit comprising the same

In a general aspect, an apparatus can include a low-side drive circuit configured to control a low-side device of a power semiconductor device pair and a high-side drive circuit configured to control a high-side device of the power semiconductor device pair. The high-side drive circuit can include an input circuit configured to receive an input signal and produce, based on the input signal, a first control signal, from which a latch set signal is produced to turn on the high-side device, and a second control signal, from which a latch reset signal is produced to turn off the high-side device. The high-side drive circuit can further include an overlap-prevention circuit configured to prevent timing overlap between the second control signal and a voltage-recovery period of the high-voltage circuit, where the voltage-recovery period occurs after turning off the high-side device of the power semiconductor device pair.

Drive circuit for power semiconductor devices

A bi-directional transmitter/receiver according to an embodiment includes a pin connected with a main control circuit, a transistor connected with a first electrode to the pin, a Schmitt trigger which determines an output according to a voltage of the pin, and a temperature sensor which is connected to the pin and which senses temperature and outputs temperature information to the pin. A driving circuit for controlling switching operation of one or more switches includes a bi-directional transmitter/receiver.

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Seoul, South Korea

Kinam Song