Intel Corporation

Kin-Yip Liu

Gary N Hammond

Sridhar Lakshmanamurthy

Kenneth D Shoemaker

Anand B Pai

James D Guilford

Prashant R Chandra

Nazar A Zaidi

Nhon Toai Quach

Tse-Yu Yeh

Charles E Narad

Ken Shoemaker

Rohit Natarajan

Chen-Chi Kuo

Yim Pun

Lawrence B Huston

Krishna M Yellamilli

Millind Mital

Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

A method and apparatus for improving network router line rate performance by an improved system for error correction is described. In an embodiment of the present invention, error correction is performed by a hardware-based system within the processing engine of a router's network processor.

Method and apparatus for improving network router line rate performance by an improved system for error checking

A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one embodiment, the special function invoked may be a feature of the processor not included in the processor's publicly known instruction set. In another embodiment, the special function invoked may cause a set of instructions to be transferred from a memory external to the processor to a memory in the processor. In such an embodiment, the method and apparatus include authenticating and decrypting the instructions before transferring from the memory external to the processor to the memory in the processor. In such an embodiment, the method and apparatus may be used for upgrading microcode within a processor by executing the special RISC instruction stored on a writeable non-volatile memory located external to the processor. In this embodiment, executing the special RISC instruction invokes resident microcode instructions on the processor to transfer microcode instructions from a memory located external to the processor to memory in the processor so that the microcode upgrade is executed in place of and/or in addition to other microcode resident in the processor. In yet another embodiment, the special RISC instruction could cause instructions to be transferred from a memory external to the processor to be transferred to the processor, decrypted, authenticated and then executed in the processor securely, privately, and without interruption.

Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode

Information in a cache that is coupled to a processor is secured by recording the location in the cache of information that is being secured, and performing a cache avoidance procedure instead of allowing the instruction to access the area of the cache containing the information being secured.

Preventing access to secure area of a cache

A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions, including macro branch instructions. The branch prediction unit is configured to receive the program instructions from the fetching unit, analyze the program instructions to identify the macro branch instructions, determine a first branch prediction for each of the macro branch instructions, and direct the fetching unit to retrieve the program instructions in an order corresponding to the first branch predictions. The decode unit is configured to receive the program instructions in the order determined by the branch prediction unit, break down the program instructions into micro-operations, and determine a decoded branch micro-operation corresponding to each of the macro branch instructions requiring verification, such that each of the decoded branch micro-operations has a decoded branch outcome of taken, if the first branch prediction is incorrect, and not taken if the first branch prediction is correct. The microprocessor may also include an execution engine configured to execute the micro-operations and determine the decoded branch outcome for each of the decoded branch micro-operations and communicate each decoded branch outcome of taken to the fetching unit such that the fetching unit can re-retrieve the program instructions in a corrected order corresponding to each incorrect first branch prediction.

Method and apparatus for branch execution on a

A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Method for scheduling a flag generating instruction and a subsequent

A microprocessor capable of renaming a numeric register and a segment register includes a plurality of general registers and a data dependency unit. The data dependency unit is configured to receive instructions to be executed, wherein the instructions include accessing the numeric register and accessing the segment register. The data dependency unit renames the numeric register as one of the plurality of general registers for each of the instructions accessing said numeric register, renames the segment register as one of the plurality of general registers for each of the instructions accessing the segment register, and generates a dependency vector for each of the instructions. The microprocessor may include a scheduler configured to receive the instructions and dependency vector and schedule the instructions for execution based on the dependency vector, and an execution engine adapted to receive the instructions from the scheduler and execute the instructions.

Growing community of inventors

San Jose, CA, United States of America

Kin-Yip Liu