Rutgers, the State University of New Jersey

Agere Systems Guardian Corp.

Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Inc.

Sematech, Inc.

Kin Ping Cheung

Pradip Kumar Roy

Yi Ma

Wei Zhu

Chun-Ting Liu

Ronald J Schutz

Chien-Shing Pai

Ruichen Liu

Byoung Hun Lee

Steven J Hillenius

Richard S Wagner

Chorng-Ping Chang

Rino Choi

Christopher J Case

Philip W Mason

Dawei Heh

Methods for determining capacitance values of a metal on semiconductor (MOS) structure are provided. A time domain reflectometry circuit may be loaded with a MOS structure. The MOS structure may be biased with various voltages, and reflectometry waveforms from the applied voltage may be collected. The capacitance of the MOS structure may be determined from the reflectometry waveforms.

Methods for measuring capacitance

A process for hermetically packaging a microscopic structure including a MEMS device is provided. The process for the present invention includes the steps of depositing a capping layer of sacrificial material patterned by lithography over the microscopic structure supported on a substrate, depositing a support layer of a dielectric material patterned by lithography over the capping layer, providing a plurality of vias through the support layer by lithography, removing the capping layer via wet etching to leave the support layer intact in the form of a shell having a cavity occupied by the microscopic structure, depositing a metal layer over the capping layer that is thick enough to provide a barrier against gas permeation, but thin enough to leave the vias open, and selectively applying under high vacuum a laser beam to the metal proximate each via for a sufficient period of time to melt the metal for sealing the via.

Processes for hermetically packaging wafer level microscopic structures

The invention relates to the measurement and monitoring of plasma-damage, and to the evaluation of the lifetime of integrated circuits under nominal operating conditions. The method calculates the intrinsic, or damage-free, lifetime of a particular transistor device by measuring the change in transconductance as a function of time for a given device over a short period of time. The change in the transconductance as a function of time, i.e., the slope of the degradation curve, is measured and then compared to a reference value. The present invention thus allows the use of hot-carrier stress method to determine plasma damage in a time efficient manner without the need of applying high acceleration voltages.

Using fast hot-carrier aging method for measuring plasma charging damage

It has been discovered that for semiconductor devices such as MOSFETs, there is significant capacitive coupling in the front-end structure, i.e., the structure from and including the device substrate up to the first metal interconnect level. The invention therefore provides a device comprising a silicon substrate, an isolation structure in the substrate (e.g., shallow trench isolation), an active device structure (e.g., a transistor structure), a dielectric layer over the active device structure, and a metal interconnect layer over the dielectric layer (metal-1 level). At least one of the dielectric components of the front-end structure comprise a material exhibiting a dielectric constant less than 3.5. This relatively low dielectric constant material reduces capacitive coupling in the front-end structure, thereby providing improved properties in the device.

Device comprising thermally stable, low dielectric constant material

The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna ratio of a semiconductor device, determines an oxide area of the semiconductor device and determines a failure fraction of the semiconductor device as a function of the oxide stress voltage and the oxide area.

Method of determining the impact of plasma-charging damage on yield and reliability in submicron integrated circuits

A method of preventing diffusion penetration of the dopant used to dope polysilicon gate material in a MOSFET is disclosed. Atomic nitrogen is introduced into the substrate prior to gate oxide growth. The nitrogen later diffuses upward into the gate oxide and blocks subsequent ion implanted gate dopants from penetrating to the substrate. Low dosages of atomic nitrogen implantation, while not significantly affecting gate oxide growth rate, produce significant improvements in the damage immunity of thin gate oxides.

Semiconductor device fabrication

Direct contact to shallow junctions in integrated circuits and interconnection between these contacts is achievable by utilizing a specific aluminum CVD process. In this process the aluminum is deposited utilizing a triisobutyl aluminum precursor onto a substrate having a nucleation layer, e.g. a titanium nitride layer. By appropriate choice of this nucleation layer to control the nucleation of the depositing aluminum, suitable contact is made while avoiding void defects present in the absence of such layer.

Process for fabricating integrated circuits having shallow junctions

Growing community of inventors

Hoboken, NJ, United States of America

Kin Ping Cheung