Sk Hynix Memory Solutions Inc.

Link a Media Devices Corporation

Seagate Technology Incorporated

Kin Ming Chan

Kwok Wah Yeung

Kin Man Ng

Meng-Kun Lee

Kwok Alfred Yeung

Ananthanarayanan Nagarajan

Shengkun Bao

Wing Fai Hui

Jason Bellorado

Marcus Marrow

Zheng Wu

Kevin Darveau Landin

Trung Thuc Nguyen

Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.

Phase locking multiple clocks of different frequencies

A setting associated with a number of command execution units to enable is received at a host controller. The host controller is used to configure a plurality of command execution units so that the number of command execution units specified by the setting are enabled. The enabled command execution units are used to process one or more commands associated with storage.

Fully scalable command execution unit

A command is received from a host. It is determined which paths in a plurality of paths are enabled. The type of command and the length associated with the command, if applicable, are determined. A path to use to perform the command is selected from the plurality of paths based at least in part on (1) which paths are determined to be enabled and one or more of the following (2) the type of the command or (2) the length associated with the command. The selected path is used to perform the command.

Hierarchical host controller for SSD device

A host access instruction is received from one of a plurality of channels which are served in parallel. The host access instruction includes an address range of one or more addresses and a type of access. The address range and type of access are compared against a table of stored address ranges and stored types of access associated with any pending host access instructions. It is determined whether to execute the host access instruction based at least in part on the comparison. If it is decided to execute the host access instruction, the host access instruction is forwarded for execution and the address range and the type of access from the host access instruction are stored in the table.

LBA blocking table for SSD controller

A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal.

Advance clocking scheme for ECC in storage

User level data associated with a location adjacent to a desired location on a magnetic disk storage is received. Media level data associated with the adjacent location is generated based at least in part on the user level data associated with the adjacent location; a processor which is configured to generate the media level data associated with the adjacent location is a same processor which is configured to generate media level data based at least in part on user level data during a write process. The media level data associated with the adjacent location is used to remove inter-track interference (ITI) associated with the adjacent location from a signal read back from the desired location.

Component reuse for ITI cancellation

An access instruction associated with accessing a target location in a disk is obtained. A number of units until the target location is accessed is calculated. It is determined whether there is time for the group of logic to transition from a lower power state to an operational state; the determination is based at least in part on the number of units between a current location of a read head associated with the hard disk system and the target location which is different from the current location of the read head and a warm up time associated with the group of logic. If it is determined there is time, the group of logic is put into the lower power state.

On demand hard disk drive system on a chip power control scheme

Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

ECC with out of order completion

A length of a separator to be skipped on the storage disk is compared with a threshold. The threshold is associated with a maximum value for which a timing loop is able to be paused without causing the timing loop to have inaccurate timing. If the length is greater than the threshold, a first split sector format is assigned to the split sector and that information is recorded. In such cases, a first portion and a second portion both include synchronization information. If the length is less than the threshold, a second split sector format is assigned to the split sector and that information is recorded. In such cases, the first portion includes synchronization information and the second portion of the split sector excludes synchronization information.

Split sector formatting of storage disks

Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame using the ECC decoder that includes a faster stage and a slower stage, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed using the ECC decoder.

Iterative ECC decoder with out of order completion

A technique for controlling a group of logic included in a hard disk drive system, is performed by obtaining an access instruction associated with accessing a target location in a disk included in the hard disk system. A number of units until the target location is accessed is calculated. It is determined whether to put the group of logic into a lower power state based at least in part on the number of units until the target location is accessed and a warm up time associated with the group of logic; in the event it is determined to do so, the group of logic is put into the lower power state.

Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. The ECC decoder includes one or more stages and at least one of the stages is coupled to a memory configured to store data associated with the at least one stage.

Formatting a storage disk is disclosed. A first portion of a sector of the storage disk is defined. The first portion precedes a defect and has a first length that varies based on a detected location of the defect. A second portion of the sector of the storage disk is defined. The second portion follows the defect and has a second length that varies based on the detected location of the defect.

Growing community of inventors

Milpitas, CA, United States of America

Kin Ming Chan