Chartered Semiconductor Manufacturing Ltd (corporation)

Other

Globalfoundries Singapore Pte. Ltd.

National University of Singapore

Nanyang Technological University

Kin-Leong Pey

Soh-Yun Siah

Lap Chan

Eng Hua Lim

Chaw Sing Ho

Kong Hean Lee

Harianto Wong

Chee Mang Ng

Wenhu Liu

Yong-Meng Lee

Nagarajan Raghavan

Generally, the subject matter disclosed herein relates to the fabrication of an RRAM cell using CMOS compatible processes. A resistance random access memory device is disclosed which includes a semiconducting substrate, a top electrode, at least one metal silicide bottom electrode formed at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below the top electrode, and at least one insulating layer positioned between the top electrode and at least a portion of the at least one bottom electrode. A method of making a resistance random access memory device is disclosed that includes forming an isolation structure in a semiconducting substrate to thereby define an enclosed area, performing at least one ion implantation process to implant dopant atoms into the substrate within the enclosed area, after performing the at least one ion implantation process, forming a layer of refractory metal above at least portions of the substrate, and performing at least one heat treatment process to form at least one metal silicide bottom electrode at least partially in the substrate, wherein at least a portion of the at least one bottom electrode is positioned below at least a portion of a top electrode of the device.

RRAM cell with bottom electrode(s) positioned in a semiconductor substrate

A method for improving the quality and uniformity of a silicide film in the fabrication of a silicided polysilicon gate and source/drain regions in an integrated circuit device is described. A polysilicon gate electrode is provided on the surface of a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate adjacent to the gate electrode. A layer of titanium is deposited over the surfaces of the substrate. The substrate is annealed whereby the titanium layer is transformed into a first titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the first titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions. A second titanium silicide layer is selectively deposited on the first titanium silicide layer to complete formation of the silicided gate electrode and source and drain regions in the fabrication of an integrated circuit device. The first titanium silicide layer reduces or eliminates the effect of the polysilicon and silicon surface effects allowing for a higher quality and more uniform second titanium silicide layer.

Selective CVD TiSi2 deposition with TiSi2 liner

This invention relates to the fabrication of integrated circuit devices and more particularly to a method for minimizing the localized mechanical stress problems that can occur when silicided polysilicon gates are used to fabricate narrow channel CMOS devices. The invention addresses the avoidance of typical stress-induced problems in polysilicon gates, such as non-uniform silicide (including bowing, thinning edges, etc.) and voids, which are becoming increasingly worse as gate lengths continue to be reduced. The key to this invention is to spread the highly detrimental mechanical stresses, in narrow silicided gates, over a larger vertical surface area. This is accomplished by using a thin/thick double polysilicon stack for the gate, whereby, the lower thin polysilicon gate layer is not silicided and the upper thick polysilicon layer is subsequently silicided. An insulating layer is used to prevent silicidation of the lower thin polysilicon gate, during silicidation of active source-drain regions. The same insulating layer is also used to avoid another cause of mechanical stress, by protecting the surface grain boundaries of the lower thin polysilicon gate layer from being stuffed with polymer during the dry etching used for spacer formation. The tall stacked gate structure allows the silicide-induced stresses to be more safely located farther away from the active devices.

Method to fabricate a double-polysilicon gate structure for a sub-quarter micron self-aligned-titanium silicide process

A method for a salicide process where S/D silicide contacts are formed in a separate silicide step than the gate silicide contacts. Preferably, TiSi.sub.2 is formed on S/D regions and TiSi.sub.2 or CoSi.sub.2 is formed on Poly electrodes (lines or gates) by etching back a sidewall spacer on the poly electrodes. The invention has two silicide steps. The TiSi.sub.2 is formed over the S/D regions while the gate electrode is protected by a silicon nitride Cap layer. Next, an ILD layer formed over the S/D regions. The interlevel dielectric (ILD) layer, cap layer and spacers on the sidewalls of the gate electrodes are etched back. The invention has two embodiments for the composition of the spacers. In a second silicide step, Titanium silicide (TiSi.sub.x or TiSi.sub.2) or Cobalt silicide (CoSi.sub.x or CoSi.sub.2) is formed on the top and sidewalls of the electrodes. A key feature of the invention is that the gate contact silicide is formed on the top and sidewalls of the electrodes.

Salicide formation on narrow poly lines by pulling back of spacer

Selective CVD TiSi.sub.2 deposition with TiSi.sub.2 liner

A method for forming self-aligned, metal silicide, (salicide), layers, on polysilicon gate structures, and on source/drain regions, located in a first region of a semiconductor substrate, while avoiding the salicide formation, on polysilicon gate structures, and on source/drain regions, located in a second region of a semiconductor substrate, has been developed. A composite insulator shape, comprising an overlying silicon nitride layer, and an underlying TEOS deposited, silicon oxide layer, is used to block polysilicon, as well as silicon regions, in the second region of the semiconductor substrate, from salicide formation. Unwanted silicon oxide spacers, created on the sides of polysilicon gate structures, during the patterning of the composite insulator shape, is selectively removed using dilute hydrofluoric acid solutions.

Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron

An in-line non-destructive method is described for identifying phases in a micro-structure such as a fine line pattern. This is accomplished by observing the Raman spectrum of the micro-structure. A particular application is a silicide layer, prepared using the SALICIDE process, where the crystal phases before and after Rapid Thermal Anneal are often different. This is reflected by the appearance of different lines in the Raman spectra so that the fraction of each phase can be determined. If the silicide layer agglomerated during the anneal, this is also detected by the Raman spectrum. The method has been used successfully down to line widths of about 0.35 microns.

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Singapore, Singapore

Kin-Leong Pey