Wang Laboratories, Inc.

Kin L Cheung

Robert P Ryan

Jeffrey W Einarson

Arthur B Barrow

Shams A Khan

In a multi-processor virtual memory system 10 a Reference and Change Table (RCT) 36 is located upon a Memory Control Unit (MCU) 25. The RCT 36 is responsive to accesses to any of the Memory Modules (MMs) 24-26 and generates and maintains status bits indicative of the reference and change activity of all of page frames of the system memory that are accessible by any of the CPUs 12A-12n. In that each of the CPUs 12A-12n has access to the page frames of the system memory each of the CPUs 12A-12n is further enabled, via privileged instructions, to test (read) and reset (clear) over a system bus 16 the memory page frame status bits that are generated and stored by the RCT 36. As such, the RCT provides to multiple data processors a centralized and readily accessible store of status information relating to page frames of the system memory.

Reference and change table storage system for virtual memory data

Instruction prefetching apparatus particularly adapted to executing an EXECUTE instruction specifiying a single subject instruction. The apparatus includes a first and second separately-controllable instruction syllable register and control apparatus. Under control of the control apparatus, the first instruction syllable register receives only the first syllable of the prefetched instruction; the second instruction syllable register receives all other syllables. The instruction syllable registers may be loaded either directly from memory or from a data register internal to the CPU. In the first case, the address of the instruction syllable to be prefetched is contained in a special instruction address register which is incremented each time an instruction syllable register is loaded. In the second case, the loading does not affect the value of the instruction address register. Also disclosed is a method of prefetching in which the first instruction syllable is prefetched into the first instruction syllable register and each of the other syllables is prefetched in turn to the second instruction syllable register and a method of executing the EXECUTE instruction in which the syllables of the EXECUTE instruction are prefetched directly from memory using the instruction address and the syllables of the subject instruction are fetched into the data register and from there into the instruction syllable registers.

Instruction prefetcher

A distributed reference and change table 36 for a virtual memory system 10 has a number of storage locations at least equal to the maximum number of data blocks of an associated read/write physical memory. A memory module 24 has a plurality of data words organized into n number of data blocks. The memory module includes an integral reference and change table having at least n storage locations each having at least two bits, one bit indicating the occurrence of an access (reference) to a corresponding data block and the other bit indicating if the access was a write (or change) type of access. A plurality of such memory modules are physically and electrically coupled to a common memory carrier module, each of the plurality of memory modules having an integral reference and change table.

Distributed reference and change table for a virtual memory system

A simplified cache with automatic updating for use in a memory system. The cache and the main memory receive data from a common input, and when a memory write operation is performed on data stored at a memory location for which there is a corresponding cache location, the data is written simultaneously to the cache and to the main memory. Since a cache location coresponding to a memory location always contains a copy of the data at the memory location, there is no need for dirty bits or valid bits in the cache resisters and the associated logic in the cache control. The main memory used with the invention may receive data either from a CPU or from I/O devices, and the cache includes apparatus permitting the CPU to perform cache read operations while the main memory is receiving data from an I/O device.

Simplified cache with automatic update

A communication network (10) has a memory unit (20) accessable to all ports (16-0, 16-1, 16-2, 16-3) of the link with a plurality of local sections (62) each associated with one of the ports. Interconnections include a dual memory bus (28) with a common bus subsystem (36) providing access to a common memory section and a local bus subsystem (30) providing access to the local memory sections, the subsystems constructed to permit concurrent independent use. Memory access priority circuitry (68) designates for each memory operating cycle a port for current service and makes memory access available to other elements when not required by the designated port.

Growing community of inventors

North Andover, MA, United States of America

Kin L Cheung