Altera Corporation

Kin Hong Au

Yan Chong

Joseph Huang

Khai Nguyen

Sean Shau-Tu Lu

Ket Chiew Sia

Ee Mei Ooi

Chi Mun Ho

An integrated circuit having a clock synchronizing circuit is described. The clock synchronizing circuit includes an input-output buffer and a plurality of sampling buffer circuits. The input-output buffer receives an input signal and generating an output signal. Each sampling buffer circuit receives the output signal and a sampling clock signal. Each sampling buffer circuit generates a first sampled output by sampling the output signal at the rising edge of the corresponding sampling clock signal and a second sampled output by sampling the output signal on the falling edge of the corresponding sampling clock signal. The sampling clock signal has a predetermined phase difference at each of the plurality of sampling buffer circuits.

Methods and structures for compensating and tracking process, voltage and temperature variations

An integrated circuit includes a clock circuit that may be used to provide clock signals to multiple input-output circuits. The integrated circuit may also include different clock structures. As an example, one of the clock structures may have multiple clock paths of substantially equal lengths while another clock structure may have a fly-by clock path. The multiple clock paths may be used to convey a subset of the clock signals to the input-output circuits. Similarly, the fly-by clock path may be used to transmit a second subset of the clock signals to the input-output circuits.

Clock structure with calibration circuitry

An integrated circuit may include a delay circuit that receives an input signal at a first logic level and produces a delayed output signal at a second logic level at an output terminal. The integrated circuit may include a preset circuit coupled to the delay circuit. The preset circuit may receive the input signal and pre-drive the delayed output signal to an intermediate logic level that lies between the first and second logic levels.

Configurable delay circuitry with compensated delay

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Perai, Malaysia

Kin Hong Au