Telefonaktiebolaget Lm Ericsson (Publ)

St-Ericsson Sa

Optis Circuit Technology, LLC

Kimmo Koli

Sami Vilhonen

Janne Peltonen

A switched mode power supply comprises a control signal generator arranged to generate first and second control signals via first and second outputs, respectively, which are coupled to respective first and second inputs of a switching stage, by means of respective first and second control signal paths. The switching stage is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element by coupling it alternately to first and second supply voltages. An adjustable delay stage in one of the first and second signal paths is arranged to control an adjustable delay so that a first delay experienced by the first control signal passing from the control signal generator's first output to the switching stage's first input is substantially equal to a second delay experienced by the second control signal passing from the control signal generator's second output to the switching stage's second input.

Switched mode power supply

A switched mode power supply () comprises a reactive element () and a control signal generator () is arranged to generate a first control signal at a first output () of the control signal generator () and a second control signal at a second output () of the control signal generator (). The first output () of the control signal generator () is coupled to a first input () of a switching stage () by means of a first control signal path () and the second output () of the control signal generator () is coupled to a second input () of the switching stage () by means of a second control signal path (). The switching stage () is arranged to, responsive to the first and second control signals, alternately charge and discharge the reactive element () by coupling it alternately to first and second supply voltages. A delay detector () is arranged to generate a delay indicator signal indicative of a relative delay between the first control signal at the first input () of the switching stage () and the second control signal at the second input () of the switching stage (). An adjustable delay stage () in one of the first and second signal paths () is arranged to, responsive to the delay indicator signal, control an adjustable delay so that a first delay experienced by the first control signal passing from the first output () of the control signal generator () to the first input () of the switching stage () is substantially equal to a second delay experienced by the second control signal passing from the second output () of the control signal generator () to the second input () of the switching stage ().

A receiver for an N-wire digital interface, where N is any integer exceeding two, has N input terminals, a common node and N detection stages. Each of the N detection stages has a resistive element coupled between the common node and a respective one of the N input terminals, and a comparator having a first input coupled to the respective one of the N input terminals and a second input coupled to the common node.

N-wire two-level digital interface

A receiver for a three-wire digital interface, a method for operating a three-wire digital interface, a signalling system comprising the receiver, and a wireless communication device comprising the signalling system. The receiver for a three-wire digital interface comprises a first resistive element coupled between a first input terminal and a first junction node, a second resistive element coupled between a second input terminal and a second junction node, and a third resistive element coupled between a third input terminal and a third junction node. A network comprising first second and third network terminals is coupled to first, second and third junction nodes. The network has substantially the same impedance between all pairs of the first, second and third network terminals.

Three-wire three-level digital interface

A signal filter () comprises a first transferred impedance filter, TIF, (TIF) having four differential signal paths (P, P, P, P) and a second TIF (TIF) having four differential signal paths (P, P, P, P)- A first differential signal port of the first TIF () is coupled to a first differential signal port of the second TIF (). A first clock generator () is arranged to provide first-TIF clock signals (CLK, CLK, CLK, CLK) having four non-overlapping phases for selecting the respective first-TIF differential signal paths (P, P, P, P), and a second clock generator () is arranged to provide second-TIF clock signals (CLK, CLK, CLK, CLK) having four non-overlapping phases for selecting the respective second-TIF differential signal paths (P, P, P, P). The phases of the second-TIF clock signals (CLK, CLK, CLK, CLK) are equal to the phases of the first-TIF clock signals (CLK, CLK, CLK, CLK) delayed by 45 degrees. The first-TIF first, second, third and fourth clock signals (CLK, CLK, CLK, CLK) and the second-TIF first, second, third and fourth clock signals (CLK, CLK, CLK, CLK) have a duty cycle in the range 16.75% to 25%.

Signal filtering

A continuous-time MASH sigma-delta analogue-to-digital converter ADC. The ADC may include first and second modulators and an output stage. The ADC may be provided with a first modulator with 1.5 bit and a second modulator with 1 bit each receiving also the feedback from the other modulator. Sampling is at higher rate at the second modulator and decimation is performed before summing its output to the output of the first modulator.

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Turku, Finland

Kimmo Koli